verilog-ethernet/example at a743f6f789a095105bf0ea21e60dc149c9eca434 - verilog-ethernet - Gitea: Git with a cup of tea

FPGA/verilog-ethernet

mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-14 06:43:18 +08:00

History

Alex Forencich 07b4efa9ba Switch out Xilinx PHY core in ExaNIC X10 example design

2019-01-18 13:49:46 -08:00

..

ADM_PCIE_9V3/fpga_10g

Switch out Xilinx PHY core in ADM-PCIE-9V3 example design

2019-01-18 13:32:58 -08:00

Update example designs

2018-11-08 09:17:29 -08:00

Update example designs

2018-11-08 09:17:29 -08:00

ExaNIC_X10/fpga

Switch out Xilinx PHY core in ExaNIC X10 example design

2019-01-18 13:49:46 -08:00

Update example designs

2018-11-08 09:17:29 -08:00

Update example designs

2018-11-08 09:17:29 -08:00

NexysVideo/fpga

Update example designs

2018-11-08 09:17:29 -08:00

Update example designs

2018-11-08 09:20:33 -08:00

Update example designs

2018-11-08 09:20:33 -08:00