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FPGA
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verilog-ethernet
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verilog-ethernet
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example
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ATLYS
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fpga
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Alex Forencich
77d22bfde0
Rework sim_build output directory, fix default makefile target
2020-12-29 14:47:12 -08:00
..
common
Add example design for Digilent Atlys board
2015-02-28 20:05:05 -08:00
fpga
Use common sync_reset module files
2020-03-27 18:27:45 -07:00
lib
Add example design for Digilent Atlys board
2015-02-28 20:05:05 -08:00
rtl
Change default target parameter
2020-12-25 01:48:24 -08:00
tb
/fpga_core
Rework sim_build output directory, fix default makefile target
2020-12-29 14:47:12 -08:00
clock.ucf
Update Atlys example design
2017-05-31 19:35:40 -07:00
fpga.ucf
Update Atlys example design
2017-05-31 19:35:40 -07:00
Makefile
Update example design
2016-01-08 01:32:04 -08:00
