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65 lines
1.9 KiB
Verilog
65 lines
1.9 KiB
Verilog
/*
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Copyright (c) 2014 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* LocalLink to AXI4-Stream bridge
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*/
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module ll_axis_bridge #
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(
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parameter DATA_WIDTH = 8
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)
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(
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input wire clk,
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input wire rst,
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/*
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* LocalLink input
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*/
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input wire [DATA_WIDTH-1:0] ll_data_in,
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input wire ll_sof_in_n,
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input wire ll_eof_in_n,
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input wire ll_src_rdy_in_n,
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output wire ll_dst_rdy_out_n,
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/*
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* AXI output
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*/
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output wire [DATA_WIDTH-1:0] axis_tdata,
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output wire axis_tvalid,
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input wire axis_tready,
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output wire axis_tlast
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);
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assign axis_tdata = ll_data_in;
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assign axis_tvalid = ~ll_src_rdy_in_n;
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assign axis_tlast = ~ll_eof_in_n;
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assign ll_dst_rdy_out_n = ~axis_tready;
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endmodule
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