FPGA/verilog-ethernet
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verilog-ethernet/example/VCU118
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Alex Forencich aaeeb05ac0 Fix PHY configuration connections 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-08-25 00:09:38 -07:00
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fpga_1g
Add TX and RX enable inputs to MACs
2023-08-24 01:24:33 -07:00
fpga_25g
Fix PHY configuration connections
2023-08-25 00:09:38 -07:00
fpga_fmc_htg_6qsfp_25g
Fix PHY configuration connections
2023-08-25 00:09:38 -07:00