FPGA/verilog-ethernet
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verilog-ethernet/example/fb2CG/fpga_25g/rtl
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Alex Forencich aaeeb05ac0 Fix PHY configuration connections 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-08-25 00:09:38 -07:00
..
eth_xcvr_phy_wrapper.v
Fix PHY configuration connections
2023-08-25 00:09:38 -07:00
fpga_core.v
Add TX and RX enable inputs to MACs
2023-08-24 01:24:33 -07:00
fpga.v
Fix PHY configuration connections
2023-08-25 00:09:38 -07:00
led_sreg_driver.v
Use unified 10G/25G design for fb2CG@KU15P
2023-07-13 21:34:53 -07:00
sync_signal.v
Use unified 10G/25G design for fb2CG@KU15P
2023-07-13 21:34:53 -07:00