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verilog-ethernet/tb/axis_fifo
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Alex Forencich ac2c0fdac8 Read configuration directly from DUT 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-08-14 16:57:30 -07:00
..
Makefile
Add pause functionality to FIFO modules
2023-08-14 16:57:16 -07:00
test_axis_fifo.py
Read configuration directly from DUT
2023-08-14 16:57:30 -07:00