mirror of
https://github.com/alexforencich/verilog-ethernet.git
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185 lines
5.7 KiB
Verilog
185 lines
5.7 KiB
Verilog
/*
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Copyright (c) 2014-2017 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI4-Stream SRL-based FIFO
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*/
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module axis_srl_fifo #
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(
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parameter DATA_WIDTH = 8,
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parameter KEEP_ENABLE = (DATA_WIDTH>8),
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parameter KEEP_WIDTH = (DATA_WIDTH/8),
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parameter LAST_ENABLE = 1,
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parameter ID_ENABLE = 0,
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parameter ID_WIDTH = 8,
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parameter DEST_ENABLE = 0,
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parameter DEST_WIDTH = 8,
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parameter USER_ENABLE = 1,
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parameter USER_WIDTH = 1,
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parameter DEPTH = 16
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI input
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*/
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input wire [DATA_WIDTH-1:0] input_axis_tdata,
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input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
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input wire input_axis_tvalid,
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output wire input_axis_tready,
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input wire input_axis_tlast,
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input wire [ID_WIDTH-1:0] input_axis_tid,
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input wire [DEST_WIDTH-1:0] input_axis_tdest,
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input wire [USER_WIDTH-1:0] input_axis_tuser,
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/*
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* AXI output
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*/
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output wire [DATA_WIDTH-1:0] output_axis_tdata,
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output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
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output wire output_axis_tvalid,
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input wire output_axis_tready,
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output wire output_axis_tlast,
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output wire [ID_WIDTH-1:0] output_axis_tid,
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output wire [DEST_WIDTH-1:0] output_axis_tdest,
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output wire [USER_WIDTH-1:0] output_axis_tuser,
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/*
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* Status
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*/
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output wire [$clog2(DEPTH+1)-1:0] count
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);
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localparam KEEP_OFFSET = DATA_WIDTH;
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localparam LAST_OFFSET = KEEP_OFFSET + (KEEP_ENABLE ? KEEP_WIDTH : 0);
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localparam ID_OFFSET = LAST_OFFSET + (LAST_ENABLE ? 1 : 0);
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localparam DEST_OFFSET = ID_OFFSET + (ID_ENABLE ? ID_WIDTH : 0);
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localparam USER_OFFSET = DEST_OFFSET + (DEST_ENABLE ? DEST_WIDTH : 0);
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localparam WIDTH = USER_OFFSET + (USER_ENABLE ? USER_WIDTH : 0);
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reg [WIDTH-1:0] data_reg[DEPTH-1:0];
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reg [$clog2(DEPTH+1)-1:0] ptr_reg = 0;
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reg full_reg = 0, full_next;
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reg empty_reg = 1, empty_next;
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wire [WIDTH-1:0] input_axis;
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wire [WIDTH-1:0] output_axis = data_reg[ptr_reg-1];
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assign input_axis_tready = ~full_reg;
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generate
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assign input_axis[DATA_WIDTH-1:0] = input_axis_tdata;
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if (KEEP_ENABLE) assign input_axis[KEEP_OFFSET +: KEEP_WIDTH] = input_axis_tkeep;
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if (LAST_ENABLE) assign input_axis[LAST_OFFSET] = input_axis_tlast;
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if (ID_ENABLE) assign input_axis[ID_OFFSET +: ID_WIDTH] = input_axis_tid;
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if (DEST_ENABLE) assign input_axis[DEST_OFFSET +: DEST_WIDTH] = input_axis_tdest;
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if (USER_ENABLE) assign input_axis[USER_OFFSET +: USER_WIDTH] = input_axis_tuser;
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endgenerate
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assign output_axis_tvalid = ~empty_reg;
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assign output_axis_tdata = output_axis[DATA_WIDTH-1:0];
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assign output_axis_tkeep = KEEP_ENABLE ? output_axis[KEEP_OFFSET +: KEEP_WIDTH] : {KEEP_WIDTH{1'b1}};
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assign output_axis_tlast = LAST_ENABLE ? output_axis[LAST_OFFSET] : 1'b1;
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assign output_axis_tid = ID_ENABLE ? output_axis[ID_OFFSET +: ID_WIDTH] : {ID_WIDTH{1'b0}};
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assign output_axis_tdest = DEST_ENABLE ? output_axis[DEST_OFFSET +: DEST_WIDTH] : {DEST_WIDTH{1'b0}};
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assign output_axis_tuser = USER_ENABLE ? output_axis[USER_OFFSET +: USER_WIDTH] : {USER_WIDTH{1'b0}};
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assign count = ptr_reg;
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wire ptr_empty = ptr_reg == 0;
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wire ptr_empty1 = ptr_reg == 1;
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wire ptr_full = ptr_reg == DEPTH;
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wire ptr_full1 = ptr_reg == DEPTH-1;
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reg shift;
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reg inc;
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reg dec;
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integer i;
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initial begin
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for (i = 0; i < DEPTH; i = i + 1) begin
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data_reg[i] <= 0;
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end
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end
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always @* begin
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shift = 0;
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inc = 0;
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dec = 0;
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full_next = full_reg;
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empty_next = empty_reg;
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if (output_axis_tready & input_axis_tvalid & ~full_reg) begin
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shift = 1;
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inc = ptr_empty;
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empty_next = 0;
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end else if (output_axis_tready & output_axis_tvalid) begin
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dec = 1;
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full_next = 0;
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empty_next = ptr_empty1;
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end else if (input_axis_tvalid & input_axis_tready) begin
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shift = 1;
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inc = 1;
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full_next = ptr_full1;
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empty_next = 0;
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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ptr_reg <= 0;
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full_reg <= 0;
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empty_reg <= 1;
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end else begin
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if (inc) begin
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ptr_reg <= ptr_reg + 1;
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end else if (dec) begin
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ptr_reg <= ptr_reg - 1;
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end else begin
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ptr_reg <= ptr_reg;
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end
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full_reg <= full_next;
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empty_reg <= empty_next;
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end
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if (shift) begin
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data_reg[0] <= input_axis;
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for (i = 0; i < DEPTH-1; i = i + 1) begin
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data_reg[i+1] <= data_reg[i];
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end
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end
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end
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endmodule
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