FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-14 06:43:18 +08:00
Code Issues Projects Releases Wiki Activity
verilog-ethernet/example/520N_MX/fpga_10g/lib/eth
Alex Forencich d052264659 Add 520N-MX 10G example design
2021-11-03 00:48:06 -07:00

Symbolic link
1 line
12 B
Plaintext
Raw Blame History

../../../../
Reference in New Issue View Git Blame Copy Permalink