mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-14 06:43:18 +08:00
76 lines
2.7 KiB
Makefile
76 lines
2.7 KiB
Makefile
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# FPGA settings
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FPGA_PART = xcvu9p-flgb2104-3-e
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FPGA_TOP = fpga
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FPGA_ARCH = virtexuplus
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# Files for synthesis
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SYN_FILES = rtl/fpga.v
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SYN_FILES += rtl/fpga_core.v
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SYN_FILES += rtl/eth_xcvr_phy_wrapper.v
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SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v
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SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
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SYN_FILES += lib/eth/rtl/eth_mac_10g.v
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SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
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SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
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SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
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SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
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SYN_FILES += lib/eth/rtl/lfsr.v
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SYN_FILES += lib/eth/rtl/eth_axis_rx.v
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SYN_FILES += lib/eth/rtl/eth_axis_tx.v
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SYN_FILES += lib/eth/rtl/udp_complete_64.v
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SYN_FILES += lib/eth/rtl/udp_checksum_gen_64.v
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SYN_FILES += lib/eth/rtl/udp_64.v
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SYN_FILES += lib/eth/rtl/udp_ip_rx_64.v
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SYN_FILES += lib/eth/rtl/udp_ip_tx_64.v
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SYN_FILES += lib/eth/rtl/ip_complete_64.v
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SYN_FILES += lib/eth/rtl/ip_64.v
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SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v
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SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v
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SYN_FILES += lib/eth/rtl/ip_arb_mux.v
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SYN_FILES += lib/eth/rtl/arp.v
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SYN_FILES += lib/eth/rtl/arp_cache.v
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SYN_FILES += lib/eth/rtl/arp_eth_rx.v
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SYN_FILES += lib/eth/rtl/arp_eth_tx.v
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SYN_FILES += lib/eth/rtl/eth_arb_mux.v
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SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
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SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
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SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
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SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
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SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
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SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
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# XDC files
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XDC_FILES = fpga.xdc
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XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
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XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
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XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl
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# IP
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IP_TCL_FILES = ip/eth_xcvr_gt.tcl
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# Configuration
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CONFIG_TCL_FILES = ./config.tcl
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include ../common/vivado.mk
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program: $(FPGA_TOP).bit
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echo "open_hw" > program.tcl
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echo "connect_hw_server" >> program.tcl
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echo "open_hw_target" >> program.tcl
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echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
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echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
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echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
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echo "program_hw_devices [current_hw_device]" >> program.tcl
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echo "exit" >> program.tcl
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vivado -nojournal -nolog -mode batch -source program.tcl
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