FPGA/verilog-ethernet
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Alex Forencich fa05d4ff3c Add TX and RX enable inputs to MACs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-08-24 01:24:33 -07:00
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fpga
Add TX and RX enable inputs to MACs
2023-08-24 01:24:33 -07:00