FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-02-04 07:13:13 +08:00
Code Issues Projects Releases Wiki Activity
verilog-ethernet/example/VCU108
History
Alex Forencich 16cd84123d Add user_sma_clk pins to VCU108 and VCU118 constraints files 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-11-29 13:58:22 -08:00
..
fpga_1g
Add user_sma_clk pins to VCU108 and VCU118 constraints files
2023-11-29 13:58:22 -08:00
fpga_10g
Add user_sma_clk pins to VCU108 and VCU118 constraints files
2023-11-29 13:58:22 -08:00