mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-28 07:03:08 +08:00
881 lines
25 KiB
Verilog
881 lines
25 KiB
Verilog
/*
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Copyright (c) 2014-2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* FPGA top-level module
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*/
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module fpga (
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/*
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* Clock: 300MHz LVDS
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*/
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input wire clk_300mhz_p,
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input wire clk_300mhz_n,
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/*
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* GPIO
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*/
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output wire [1:0] user_led_g,
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output wire user_led_r,
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output wire [1:0] front_led,
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input wire [1:0] user_sw,
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/*
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* Ethernet: QSFP28
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*/
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output wire qsfp_0_tx_0_p,
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output wire qsfp_0_tx_0_n,
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input wire qsfp_0_rx_0_p,
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input wire qsfp_0_rx_0_n,
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output wire qsfp_0_tx_1_p,
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output wire qsfp_0_tx_1_n,
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input wire qsfp_0_rx_1_p,
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input wire qsfp_0_rx_1_n,
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output wire qsfp_0_tx_2_p,
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output wire qsfp_0_tx_2_n,
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input wire qsfp_0_rx_2_p,
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input wire qsfp_0_rx_2_n,
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output wire qsfp_0_tx_3_p,
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output wire qsfp_0_tx_3_n,
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input wire qsfp_0_rx_3_p,
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input wire qsfp_0_rx_3_n,
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input wire qsfp_0_mgt_refclk_p,
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input wire qsfp_0_mgt_refclk_n,
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input wire qsfp_0_modprs_l,
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output wire qsfp_0_sel_l,
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output wire qsfp_1_tx_0_p,
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output wire qsfp_1_tx_0_n,
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input wire qsfp_1_rx_0_p,
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input wire qsfp_1_rx_0_n,
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output wire qsfp_1_tx_1_p,
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output wire qsfp_1_tx_1_n,
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input wire qsfp_1_rx_1_p,
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input wire qsfp_1_rx_1_n,
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output wire qsfp_1_tx_2_p,
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output wire qsfp_1_tx_2_n,
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input wire qsfp_1_rx_2_p,
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input wire qsfp_1_rx_2_n,
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output wire qsfp_1_tx_3_p,
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output wire qsfp_1_tx_3_n,
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input wire qsfp_1_rx_3_p,
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input wire qsfp_1_rx_3_n,
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input wire qsfp_1_mgt_refclk_p,
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input wire qsfp_1_mgt_refclk_n,
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input wire qsfp_1_modprs_l,
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output wire qsfp_1_sel_l,
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output wire qsfp_reset_l,
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input wire qsfp_int_l
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);
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// Clock and reset
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wire clk_300mhz_ibufg;
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wire clk_125mhz_mmcm_out;
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// Internal 125 MHz clock
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wire clk_125mhz_int;
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wire rst_125mhz_int;
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// Internal 156.25 MHz clock
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wire clk_156mhz_int;
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wire rst_156mhz_int;
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wire mmcm_rst = 1'b0;
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wire mmcm_locked;
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wire mmcm_clkfb;
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IBUFGDS #(
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.DIFF_TERM("FALSE"),
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.IBUF_LOW_PWR("FALSE")
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)
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clk_300mhz_ibufg_inst (
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.O (clk_300mhz_ibufg),
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.I (clk_300mhz_p),
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.IB (clk_300mhz_n)
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);
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// MMCM instance
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// 300 MHz in, 125 MHz out
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// PFD range: 10 MHz to 500 MHz
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// VCO range: 800 MHz to 1600 MHz
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// M = 10, D = 3 sets Fvco = 1000 MHz (in range)
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// Divide by 8 to get output frequency of 125 MHz
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MMCME3_BASE #(
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.BANDWIDTH("OPTIMIZED"),
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.CLKOUT0_DIVIDE_F(8),
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT0_PHASE(0),
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.CLKOUT1_DIVIDE(1),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT1_PHASE(0),
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.CLKOUT2_DIVIDE(1),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT2_PHASE(0),
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.CLKOUT3_DIVIDE(1),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT3_PHASE(0),
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.CLKOUT4_DIVIDE(1),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT4_PHASE(0),
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.CLKOUT5_DIVIDE(1),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT5_PHASE(0),
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.CLKOUT6_DIVIDE(1),
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.CLKOUT6_DUTY_CYCLE(0.5),
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.CLKOUT6_PHASE(0),
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.CLKFBOUT_MULT_F(10),
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.CLKFBOUT_PHASE(0),
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.DIVCLK_DIVIDE(3),
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.REF_JITTER1(0.010),
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.CLKIN1_PERIOD(3.333),
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.STARTUP_WAIT("FALSE"),
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.CLKOUT4_CASCADE("FALSE")
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)
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clk_mmcm_inst (
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.CLKIN1(clk_300mhz_ibufg),
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.CLKFBIN(mmcm_clkfb),
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.RST(mmcm_rst),
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.PWRDWN(1'b0),
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.CLKOUT0(clk_125mhz_mmcm_out),
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.CLKOUT0B(),
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.CLKOUT1(),
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.CLKOUT1B(),
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.CLKOUT2(),
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.CLKOUT2B(),
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.CLKOUT3(),
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.CLKOUT3B(),
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.CLKOUT4(),
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.CLKOUT5(),
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.CLKOUT6(),
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.CLKFBOUT(mmcm_clkfb),
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.CLKFBOUTB(),
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.LOCKED(mmcm_locked)
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);
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BUFG
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clk_125mhz_bufg_inst (
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.I(clk_125mhz_mmcm_out),
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.O(clk_125mhz_int)
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);
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sync_reset #(
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.N(4)
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)
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sync_reset_125mhz_inst (
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.clk(clk_125mhz_int),
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.rst(~mmcm_locked),
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.out(rst_125mhz_int)
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);
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// GPIO
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wire [1:0] user_sw_int;
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debounce_switch #(
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.WIDTH(2),
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.N(4),
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.RATE(125000)
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)
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debounce_switch_inst (
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.clk(clk_125mhz_int),
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.rst(rst_125mhz_int),
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.in({user_sw}),
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.out({user_sw_int})
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);
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// XGMII 10G PHY
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assign qsfp_0_sel_l = 1'b0;
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wire qsfp_0_tx_clk_0_int;
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wire qsfp_0_tx_rst_0_int;
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wire [63:0] qsfp_0_txd_0_int;
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wire [7:0] qsfp_0_txc_0_int;
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wire qsfp_0_rx_clk_0_int;
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wire qsfp_0_rx_rst_0_int;
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wire [63:0] qsfp_0_rxd_0_int;
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wire [7:0] qsfp_0_rxc_0_int;
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wire qsfp_0_tx_clk_1_int;
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wire qsfp_0_tx_rst_1_int;
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wire [63:0] qsfp_0_txd_1_int;
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wire [7:0] qsfp_0_txc_1_int;
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wire qsfp_0_rx_clk_1_int;
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wire qsfp_0_rx_rst_1_int;
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wire [63:0] qsfp_0_rxd_1_int;
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wire [7:0] qsfp_0_rxc_1_int;
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wire qsfp_0_tx_clk_2_int;
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wire qsfp_0_tx_rst_2_int;
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wire [63:0] qsfp_0_txd_2_int;
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wire [7:0] qsfp_0_txc_2_int;
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wire qsfp_0_rx_clk_2_int;
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wire qsfp_0_rx_rst_2_int;
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wire [63:0] qsfp_0_rxd_2_int;
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wire [7:0] qsfp_0_rxc_2_int;
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wire qsfp_0_tx_clk_3_int;
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wire qsfp_0_tx_rst_3_int;
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wire [63:0] qsfp_0_txd_3_int;
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wire [7:0] qsfp_0_txc_3_int;
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wire qsfp_0_rx_clk_3_int;
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wire qsfp_0_rx_rst_3_int;
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wire [63:0] qsfp_0_rxd_3_int;
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wire [7:0] qsfp_0_rxc_3_int;
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assign qsfp_1_sel_l = 1'b0;
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wire qsfp_1_tx_clk_0_int;
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wire qsfp_1_tx_rst_0_int;
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wire [63:0] qsfp_1_txd_0_int;
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wire [7:0] qsfp_1_txc_0_int;
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wire qsfp_1_rx_clk_0_int;
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wire qsfp_1_rx_rst_0_int;
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wire [63:0] qsfp_1_rxd_0_int;
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wire [7:0] qsfp_1_rxc_0_int;
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wire qsfp_1_tx_clk_1_int;
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wire qsfp_1_tx_rst_1_int;
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wire [63:0] qsfp_1_txd_1_int;
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wire [7:0] qsfp_1_txc_1_int;
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wire qsfp_1_rx_clk_1_int;
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wire qsfp_1_rx_rst_1_int;
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wire [63:0] qsfp_1_rxd_1_int;
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wire [7:0] qsfp_1_rxc_1_int;
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wire qsfp_1_tx_clk_2_int;
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wire qsfp_1_tx_rst_2_int;
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wire [63:0] qsfp_1_txd_2_int;
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wire [7:0] qsfp_1_txc_2_int;
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wire qsfp_1_rx_clk_2_int;
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wire qsfp_1_rx_rst_2_int;
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wire [63:0] qsfp_1_rxd_2_int;
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wire [7:0] qsfp_1_rxc_2_int;
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wire qsfp_1_tx_clk_3_int;
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wire qsfp_1_tx_rst_3_int;
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wire [63:0] qsfp_1_txd_3_int;
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wire [7:0] qsfp_1_txc_3_int;
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wire qsfp_1_rx_clk_3_int;
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wire qsfp_1_rx_rst_3_int;
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wire [63:0] qsfp_1_rxd_3_int;
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wire [7:0] qsfp_1_rxc_3_int;
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assign qsfp_reset_l = 1'b1;
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wire qsfp_0_rx_block_lock_0;
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wire qsfp_0_rx_block_lock_1;
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wire qsfp_0_rx_block_lock_2;
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wire qsfp_0_rx_block_lock_3;
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wire qsfp_1_rx_block_lock_0;
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wire qsfp_1_rx_block_lock_1;
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wire qsfp_1_rx_block_lock_2;
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wire qsfp_1_rx_block_lock_3;
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wire qsfp_0_mgt_refclk;
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wire qsfp_1_mgt_refclk;
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wire [7:0] gt_txclkout;
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wire gt_txusrclk;
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wire [7:0] gt_rxclkout;
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wire [7:0] gt_rxusrclk;
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wire gt_reset_tx_done;
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wire gt_reset_rx_done;
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wire [7:0] gt_txprgdivresetdone;
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wire [7:0] gt_txpmaresetdone;
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wire [7:0] gt_rxprgdivresetdone;
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wire [7:0] gt_rxpmaresetdone;
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wire gt_tx_reset = ~((>_txprgdivresetdone) & (>_txpmaresetdone));
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wire gt_rx_reset = ~>_rxpmaresetdone;
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reg gt_userclk_tx_active = 1'b0;
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reg [7:0] gt_userclk_rx_active = 1'b0;
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IBUFDS_GTE4 ibufds_gte4_qsfp_0_mgt_refclk_inst (
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.I (qsfp_0_mgt_refclk_p),
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.IB (qsfp_0_mgt_refclk_n),
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.CEB (1'b0),
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.O (qsfp_0_mgt_refclk),
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.ODIV2 ()
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);
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IBUFDS_GTE4 ibufds_gte4_qsfp_1_mgt_refclk_inst (
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.I (qsfp_1_mgt_refclk_p),
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.IB (qsfp_1_mgt_refclk_n),
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.CEB (1'b0),
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.O (qsfp_1_mgt_refclk),
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.ODIV2 ()
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);
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BUFG_GT bufg_gt_tx_usrclk_inst (
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.CE (1'b1),
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.CEMASK (1'b0),
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.CLR (gt_tx_reset),
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.CLRMASK (1'b0),
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.DIV (3'd0),
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.I (gt_txclkout[0]),
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.O (gt_txusrclk)
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);
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assign clk_156mhz_int = gt_txusrclk;
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always @(posedge gt_txusrclk, posedge gt_tx_reset) begin
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if (gt_tx_reset) begin
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gt_userclk_tx_active <= 1'b0;
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end else begin
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gt_userclk_tx_active <= 1'b1;
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end
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end
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generate
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genvar n;
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for (n = 0; n < 8; n = n + 1) begin
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BUFG_GT bufg_gt_rx_usrclk_inst (
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.CE (1'b1),
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.CEMASK (1'b0),
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.CLR (gt_rx_reset),
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.CLRMASK (1'b0),
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.DIV (3'd0),
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.I (gt_rxclkout[n]),
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.O (gt_rxusrclk[n])
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);
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always @(posedge gt_rxusrclk[n], posedge gt_rx_reset) begin
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if (gt_rx_reset) begin
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gt_userclk_rx_active[n] <= 1'b0;
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end else begin
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gt_userclk_rx_active[n] <= 1'b1;
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end
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end
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end
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endgenerate
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sync_reset #(
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.N(4)
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)
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sync_reset_156mhz_inst (
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.clk(clk_156mhz_int),
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.rst(~gt_reset_tx_done),
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.out(rst_156mhz_int)
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);
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wire [5:0] qsfp_0_gt_txheader_0;
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wire [63:0] qsfp_0_gt_txdata_0;
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wire qsfp_0_gt_rxgearboxslip_0;
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wire [5:0] qsfp_0_gt_rxheader_0;
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wire [1:0] qsfp_0_gt_rxheadervalid_0;
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wire [63:0] qsfp_0_gt_rxdata_0;
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wire [1:0] qsfp_0_gt_rxdatavalid_0;
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wire [5:0] qsfp_0_gt_txheader_1;
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wire [63:0] qsfp_0_gt_txdata_1;
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wire qsfp_0_gt_rxgearboxslip_1;
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wire [5:0] qsfp_0_gt_rxheader_1;
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wire [1:0] qsfp_0_gt_rxheadervalid_1;
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wire [63:0] qsfp_0_gt_rxdata_1;
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wire [1:0] qsfp_0_gt_rxdatavalid_1;
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wire [5:0] qsfp_0_gt_txheader_2;
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wire [63:0] qsfp_0_gt_txdata_2;
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wire qsfp_0_gt_rxgearboxslip_2;
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wire [5:0] qsfp_0_gt_rxheader_2;
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wire [1:0] qsfp_0_gt_rxheadervalid_2;
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wire [63:0] qsfp_0_gt_rxdata_2;
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wire [1:0] qsfp_0_gt_rxdatavalid_2;
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wire [5:0] qsfp_0_gt_txheader_3;
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wire [63:0] qsfp_0_gt_txdata_3;
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wire qsfp_0_gt_rxgearboxslip_3;
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wire [5:0] qsfp_0_gt_rxheader_3;
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wire [1:0] qsfp_0_gt_rxheadervalid_3;
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wire [63:0] qsfp_0_gt_rxdata_3;
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wire [1:0] qsfp_0_gt_rxdatavalid_3;
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wire [5:0] qsfp_1_gt_txheader_0;
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wire [63:0] qsfp_1_gt_txdata_0;
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wire qsfp_1_gt_rxgearboxslip_0;
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wire [5:0] qsfp_1_gt_rxheader_0;
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wire [1:0] qsfp_1_gt_rxheadervalid_0;
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wire [63:0] qsfp_1_gt_rxdata_0;
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wire [1:0] qsfp_1_gt_rxdatavalid_0;
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wire [5:0] qsfp_1_gt_txheader_1;
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wire [63:0] qsfp_1_gt_txdata_1;
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wire qsfp_1_gt_rxgearboxslip_1;
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wire [5:0] qsfp_1_gt_rxheader_1;
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wire [1:0] qsfp_1_gt_rxheadervalid_1;
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wire [63:0] qsfp_1_gt_rxdata_1;
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wire [1:0] qsfp_1_gt_rxdatavalid_1;
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|
|
|
wire [5:0] qsfp_1_gt_txheader_2;
|
|
wire [63:0] qsfp_1_gt_txdata_2;
|
|
wire qsfp_1_gt_rxgearboxslip_2;
|
|
wire [5:0] qsfp_1_gt_rxheader_2;
|
|
wire [1:0] qsfp_1_gt_rxheadervalid_2;
|
|
wire [63:0] qsfp_1_gt_rxdata_2;
|
|
wire [1:0] qsfp_1_gt_rxdatavalid_2;
|
|
|
|
wire [5:0] qsfp_1_gt_txheader_3;
|
|
wire [63:0] qsfp_1_gt_txdata_3;
|
|
wire qsfp_1_gt_rxgearboxslip_3;
|
|
wire [5:0] qsfp_1_gt_rxheader_3;
|
|
wire [1:0] qsfp_1_gt_rxheadervalid_3;
|
|
wire [63:0] qsfp_1_gt_rxdata_3;
|
|
wire [1:0] qsfp_1_gt_rxdatavalid_3;
|
|
|
|
gtwizard_ultrascale_0
|
|
qsfp_gty_inst (
|
|
.gtwiz_userclk_tx_active_in(>_userclk_tx_active),
|
|
.gtwiz_userclk_rx_active_in(>_userclk_rx_active),
|
|
|
|
.gtwiz_reset_clk_freerun_in(clk_125mhz_int),
|
|
.gtwiz_reset_all_in(rst_125mhz_int),
|
|
|
|
.gtwiz_reset_tx_pll_and_datapath_in(1'b0),
|
|
.gtwiz_reset_tx_datapath_in(1'b0),
|
|
|
|
.gtwiz_reset_rx_pll_and_datapath_in(1'b0),
|
|
.gtwiz_reset_rx_datapath_in(1'b0),
|
|
|
|
.gtwiz_reset_rx_cdr_stable_out(),
|
|
|
|
.gtwiz_reset_tx_done_out(gt_reset_tx_done),
|
|
.gtwiz_reset_rx_done_out(gt_reset_rx_done),
|
|
|
|
.gtrefclk00_in({qsfp_0_mgt_refclk, qsfp_1_mgt_refclk}),
|
|
|
|
.qpll0outclk_out(),
|
|
.qpll0outrefclk_out(),
|
|
|
|
.gtyrxn_in({qsfp_0_rx_3_n, qsfp_0_rx_2_n, qsfp_0_rx_1_n, qsfp_0_rx_0_n, qsfp_1_rx_3_n, qsfp_1_rx_2_n, qsfp_1_rx_1_n, qsfp_1_rx_0_n}),
|
|
.gtyrxp_in({qsfp_0_rx_3_p, qsfp_0_rx_2_p, qsfp_0_rx_1_p, qsfp_0_rx_0_p, qsfp_1_rx_3_p, qsfp_1_rx_2_p, qsfp_1_rx_1_p, qsfp_1_rx_0_p}),
|
|
|
|
.rxusrclk_in(gt_rxusrclk),
|
|
.rxusrclk2_in(gt_rxusrclk),
|
|
|
|
.gtwiz_userdata_tx_in({qsfp_0_gt_txdata_3, qsfp_0_gt_txdata_2, qsfp_0_gt_txdata_1, qsfp_0_gt_txdata_0, qsfp_1_gt_txdata_3, qsfp_1_gt_txdata_2, qsfp_1_gt_txdata_1, qsfp_1_gt_txdata_0}),
|
|
.txheader_in({qsfp_0_gt_txheader_3, qsfp_0_gt_txheader_2, qsfp_0_gt_txheader_1, qsfp_0_gt_txheader_0, qsfp_1_gt_txheader_3, qsfp_1_gt_txheader_2, qsfp_1_gt_txheader_1, qsfp_1_gt_txheader_0}),
|
|
.txsequence_in({8{1'b0}}),
|
|
|
|
.txusrclk_in({8{gt_txusrclk}}),
|
|
.txusrclk2_in({8{gt_txusrclk}}),
|
|
|
|
.gtpowergood_out(),
|
|
|
|
.gtytxn_out({qsfp_0_tx_3_n, qsfp_0_tx_2_n, qsfp_0_tx_1_n, qsfp_0_tx_0_n, qsfp_1_tx_3_n, qsfp_1_tx_2_n, qsfp_1_tx_1_n, qsfp_1_tx_0_n}),
|
|
.gtytxp_out({qsfp_0_tx_3_p, qsfp_0_tx_2_p, qsfp_0_tx_1_p, qsfp_0_tx_0_p, qsfp_1_tx_3_p, qsfp_1_tx_2_p, qsfp_1_tx_1_p, qsfp_1_tx_0_p}),
|
|
|
|
.rxgearboxslip_in({qsfp_0_gt_rxgearboxslip_3, qsfp_0_gt_rxgearboxslip_2, qsfp_0_gt_rxgearboxslip_1, qsfp_0_gt_rxgearboxslip_0, qsfp_1_gt_rxgearboxslip_3, qsfp_1_gt_rxgearboxslip_2, qsfp_1_gt_rxgearboxslip_1, qsfp_1_gt_rxgearboxslip_0}),
|
|
.gtwiz_userdata_rx_out({qsfp_0_gt_rxdata_3, qsfp_0_gt_rxdata_2, qsfp_0_gt_rxdata_1, qsfp_0_gt_rxdata_0, qsfp_1_gt_rxdata_3, qsfp_1_gt_rxdata_2, qsfp_1_gt_rxdata_1, qsfp_1_gt_rxdata_0}),
|
|
.rxdatavalid_out({qsfp_0_gt_rxdatavalid_3, qsfp_0_gt_rxdatavalid_2, qsfp_0_gt_rxdatavalid_1, qsfp_0_gt_rxdatavalid_0, qsfp_1_gt_rxdatavalid_3, qsfp_1_gt_rxdatavalid_2, qsfp_1_gt_rxdatavalid_1, qsfp_1_gt_rxdatavalid_0}),
|
|
.rxheader_out({qsfp_0_gt_rxheader_3, qsfp_0_gt_rxheader_2, qsfp_0_gt_rxheader_1, qsfp_0_gt_rxheader_0, qsfp_1_gt_rxheader_3, qsfp_1_gt_rxheader_2, qsfp_1_gt_rxheader_1, qsfp_1_gt_rxheader_0}),
|
|
.rxheadervalid_out({qsfp_0_gt_rxheadervalid_3, qsfp_0_gt_rxheadervalid_2, qsfp_0_gt_rxheadervalid_1, qsfp_0_gt_rxheadervalid_0, qsfp_1_gt_rxheadervalid_3, qsfp_1_gt_rxheadervalid_2, qsfp_1_gt_rxheadervalid_1, qsfp_1_gt_rxheadervalid_0}),
|
|
.rxoutclk_out(gt_rxclkout),
|
|
.rxpmaresetdone_out(gt_rxpmaresetdone),
|
|
.rxprgdivresetdone_out(gt_rxprgdivresetdone),
|
|
.rxstartofseq_out(),
|
|
|
|
.txoutclk_out(gt_txclkout),
|
|
.txpmaresetdone_out(gt_txpmaresetdone),
|
|
.txprgdivresetdone_out(gt_txprgdivresetdone)
|
|
);
|
|
|
|
assign qsfp_0_tx_clk_0_int = clk_156mhz_int;
|
|
assign qsfp_0_tx_rst_0_int = rst_156mhz_int;
|
|
|
|
assign qsfp_0_rx_clk_0_int = gt_rxusrclk[4];
|
|
|
|
sync_reset #(
|
|
.N(4)
|
|
)
|
|
qsfp_0_rx_rst_0_reset_sync_inst (
|
|
.clk(qsfp_0_rx_clk_0_int),
|
|
.rst(~gt_reset_rx_done),
|
|
.out(qsfp_0_rx_rst_0_int)
|
|
);
|
|
|
|
eth_phy_10g #(
|
|
.BIT_REVERSE(1)
|
|
)
|
|
qsfp_0_phy_0_inst (
|
|
.tx_clk(qsfp_0_tx_clk_0_int),
|
|
.tx_rst(qsfp_0_tx_rst_0_int),
|
|
.rx_clk(qsfp_0_rx_clk_0_int),
|
|
.rx_rst(qsfp_0_rx_rst_0_int),
|
|
.xgmii_txd(qsfp_0_txd_0_int),
|
|
.xgmii_txc(qsfp_0_txc_0_int),
|
|
.xgmii_rxd(qsfp_0_rxd_0_int),
|
|
.xgmii_rxc(qsfp_0_rxc_0_int),
|
|
.serdes_tx_data(qsfp_0_gt_txdata_0),
|
|
.serdes_tx_hdr(qsfp_0_gt_txheader_0),
|
|
.serdes_rx_data(qsfp_0_gt_rxdata_0),
|
|
.serdes_rx_hdr(qsfp_0_gt_rxheader_0),
|
|
.serdes_rx_bitslip(qsfp_0_gt_rxgearboxslip_0),
|
|
.rx_block_lock(qsfp_0_rx_block_lock_0),
|
|
.rx_high_ber()
|
|
);
|
|
|
|
assign qsfp_0_tx_clk_1_int = clk_156mhz_int;
|
|
assign qsfp_0_tx_rst_1_int = rst_156mhz_int;
|
|
|
|
assign qsfp_0_rx_clk_1_int = gt_rxusrclk[5];
|
|
|
|
sync_reset #(
|
|
.N(4)
|
|
)
|
|
qsfp_0_rx_rst_1_reset_sync_inst (
|
|
.clk(qsfp_0_rx_clk_1_int),
|
|
.rst(~gt_reset_rx_done),
|
|
.out(qsfp_0_rx_rst_1_int)
|
|
);
|
|
|
|
eth_phy_10g #(
|
|
.BIT_REVERSE(1)
|
|
)
|
|
qsfp_0_phy_1_inst (
|
|
.tx_clk(qsfp_0_tx_clk_1_int),
|
|
.tx_rst(qsfp_0_tx_rst_1_int),
|
|
.rx_clk(qsfp_0_rx_clk_1_int),
|
|
.rx_rst(qsfp_0_rx_rst_1_int),
|
|
.xgmii_txd(qsfp_0_txd_1_int),
|
|
.xgmii_txc(qsfp_0_txc_1_int),
|
|
.xgmii_rxd(qsfp_0_rxd_1_int),
|
|
.xgmii_rxc(qsfp_0_rxc_1_int),
|
|
.serdes_tx_data(qsfp_0_gt_txdata_1),
|
|
.serdes_tx_hdr(qsfp_0_gt_txheader_1),
|
|
.serdes_rx_data(qsfp_0_gt_rxdata_1),
|
|
.serdes_rx_hdr(qsfp_0_gt_rxheader_1),
|
|
.serdes_rx_bitslip(qsfp_0_gt_rxgearboxslip_1),
|
|
.rx_block_lock(qsfp_0_rx_block_lock_1),
|
|
.rx_high_ber()
|
|
);
|
|
|
|
assign qsfp_0_tx_clk_2_int = clk_156mhz_int;
|
|
assign qsfp_0_tx_rst_2_int = rst_156mhz_int;
|
|
|
|
assign qsfp_0_rx_clk_2_int = gt_rxusrclk[6];
|
|
|
|
sync_reset #(
|
|
.N(4)
|
|
)
|
|
qsfp_0_rx_rst_2_reset_sync_inst (
|
|
.clk(qsfp_0_rx_clk_2_int),
|
|
.rst(~gt_reset_rx_done),
|
|
.out(qsfp_0_rx_rst_2_int)
|
|
);
|
|
|
|
eth_phy_10g #(
|
|
.BIT_REVERSE(1)
|
|
)
|
|
qsfp_0_phy_2_inst (
|
|
.tx_clk(qsfp_0_tx_clk_2_int),
|
|
.tx_rst(qsfp_0_tx_rst_2_int),
|
|
.rx_clk(qsfp_0_rx_clk_2_int),
|
|
.rx_rst(qsfp_0_rx_rst_2_int),
|
|
.xgmii_txd(qsfp_0_txd_2_int),
|
|
.xgmii_txc(qsfp_0_txc_2_int),
|
|
.xgmii_rxd(qsfp_0_rxd_2_int),
|
|
.xgmii_rxc(qsfp_0_rxc_2_int),
|
|
.serdes_tx_data(qsfp_0_gt_txdata_2),
|
|
.serdes_tx_hdr(qsfp_0_gt_txheader_2),
|
|
.serdes_rx_data(qsfp_0_gt_rxdata_2),
|
|
.serdes_rx_hdr(qsfp_0_gt_rxheader_2),
|
|
.serdes_rx_bitslip(qsfp_0_gt_rxgearboxslip_2),
|
|
.rx_block_lock(qsfp_0_rx_block_lock_2),
|
|
.rx_high_ber()
|
|
);
|
|
|
|
assign qsfp_0_tx_clk_3_int = clk_156mhz_int;
|
|
assign qsfp_0_tx_rst_3_int = rst_156mhz_int;
|
|
|
|
assign qsfp_0_rx_clk_3_int = gt_rxusrclk[7];
|
|
|
|
sync_reset #(
|
|
.N(4)
|
|
)
|
|
qsfp_0_rx_rst_3_reset_sync_inst (
|
|
.clk(qsfp_0_rx_clk_3_int),
|
|
.rst(~gt_reset_rx_done),
|
|
.out(qsfp_0_rx_rst_3_int)
|
|
);
|
|
|
|
eth_phy_10g #(
|
|
.BIT_REVERSE(1)
|
|
)
|
|
qsfp_0_phy_3_inst (
|
|
.tx_clk(qsfp_0_tx_clk_3_int),
|
|
.tx_rst(qsfp_0_tx_rst_3_int),
|
|
.rx_clk(qsfp_0_rx_clk_3_int),
|
|
.rx_rst(qsfp_0_rx_rst_3_int),
|
|
.xgmii_txd(qsfp_0_txd_3_int),
|
|
.xgmii_txc(qsfp_0_txc_3_int),
|
|
.xgmii_rxd(qsfp_0_rxd_3_int),
|
|
.xgmii_rxc(qsfp_0_rxc_3_int),
|
|
.serdes_tx_data(qsfp_0_gt_txdata_3),
|
|
.serdes_tx_hdr(qsfp_0_gt_txheader_3),
|
|
.serdes_rx_data(qsfp_0_gt_rxdata_3),
|
|
.serdes_rx_hdr(qsfp_0_gt_rxheader_3),
|
|
.serdes_rx_bitslip(qsfp_0_gt_rxgearboxslip_3),
|
|
.rx_block_lock(qsfp_0_rx_block_lock_3),
|
|
.rx_high_ber()
|
|
);
|
|
|
|
assign qsfp_1_tx_clk_0_int = clk_156mhz_int;
|
|
assign qsfp_1_tx_rst_0_int = rst_156mhz_int;
|
|
|
|
assign qsfp_1_rx_clk_0_int = gt_rxusrclk[0];
|
|
|
|
sync_reset #(
|
|
.N(4)
|
|
)
|
|
qsfp_1_rx_rst_0_reset_sync_inst (
|
|
.clk(qsfp_1_rx_clk_0_int),
|
|
.rst(~gt_reset_rx_done),
|
|
.out(qsfp_1_rx_rst_0_int)
|
|
);
|
|
|
|
eth_phy_10g #(
|
|
.BIT_REVERSE(1)
|
|
)
|
|
qsfp_1_phy_0_inst (
|
|
.tx_clk(qsfp_1_tx_clk_0_int),
|
|
.tx_rst(qsfp_1_tx_rst_0_int),
|
|
.rx_clk(qsfp_1_rx_clk_0_int),
|
|
.rx_rst(qsfp_1_rx_rst_0_int),
|
|
.xgmii_txd(qsfp_1_txd_0_int),
|
|
.xgmii_txc(qsfp_1_txc_0_int),
|
|
.xgmii_rxd(qsfp_1_rxd_0_int),
|
|
.xgmii_rxc(qsfp_1_rxc_0_int),
|
|
.serdes_tx_data(qsfp_1_gt_txdata_0),
|
|
.serdes_tx_hdr(qsfp_1_gt_txheader_0),
|
|
.serdes_rx_data(qsfp_1_gt_rxdata_0),
|
|
.serdes_rx_hdr(qsfp_1_gt_rxheader_0),
|
|
.serdes_rx_bitslip(qsfp_1_gt_rxgearboxslip_0),
|
|
.rx_block_lock(qsfp_1_rx_block_lock_0),
|
|
.rx_high_ber()
|
|
);
|
|
|
|
assign qsfp_1_tx_clk_1_int = clk_156mhz_int;
|
|
assign qsfp_1_tx_rst_1_int = rst_156mhz_int;
|
|
|
|
assign qsfp_1_rx_clk_1_int = gt_rxusrclk[1];
|
|
|
|
sync_reset #(
|
|
.N(4)
|
|
)
|
|
qsfp_1_rx_rst_1_reset_sync_inst (
|
|
.clk(qsfp_1_rx_clk_1_int),
|
|
.rst(~gt_reset_rx_done),
|
|
.out(qsfp_1_rx_rst_1_int)
|
|
);
|
|
|
|
eth_phy_10g #(
|
|
.BIT_REVERSE(1)
|
|
)
|
|
qsfp_1_phy_1_inst (
|
|
.tx_clk(qsfp_1_tx_clk_1_int),
|
|
.tx_rst(qsfp_1_tx_rst_1_int),
|
|
.rx_clk(qsfp_1_rx_clk_1_int),
|
|
.rx_rst(qsfp_1_rx_rst_1_int),
|
|
.xgmii_txd(qsfp_1_txd_1_int),
|
|
.xgmii_txc(qsfp_1_txc_1_int),
|
|
.xgmii_rxd(qsfp_1_rxd_1_int),
|
|
.xgmii_rxc(qsfp_1_rxc_1_int),
|
|
.serdes_tx_data(qsfp_1_gt_txdata_1),
|
|
.serdes_tx_hdr(qsfp_1_gt_txheader_1),
|
|
.serdes_rx_data(qsfp_1_gt_rxdata_1),
|
|
.serdes_rx_hdr(qsfp_1_gt_rxheader_1),
|
|
.serdes_rx_bitslip(qsfp_1_gt_rxgearboxslip_1),
|
|
.rx_block_lock(qsfp_1_rx_block_lock_1),
|
|
.rx_high_ber()
|
|
);
|
|
|
|
assign qsfp_1_tx_clk_2_int = clk_156mhz_int;
|
|
assign qsfp_1_tx_rst_2_int = rst_156mhz_int;
|
|
|
|
assign qsfp_1_rx_clk_2_int = gt_rxusrclk[2];
|
|
|
|
sync_reset #(
|
|
.N(4)
|
|
)
|
|
qsfp_1_rx_rst_2_reset_sync_inst (
|
|
.clk(qsfp_1_rx_clk_2_int),
|
|
.rst(~gt_reset_rx_done),
|
|
.out(qsfp_1_rx_rst_2_int)
|
|
);
|
|
|
|
eth_phy_10g #(
|
|
.BIT_REVERSE(1)
|
|
)
|
|
qsfp_1_phy_2_inst (
|
|
.tx_clk(qsfp_1_tx_clk_2_int),
|
|
.tx_rst(qsfp_1_tx_rst_2_int),
|
|
.rx_clk(qsfp_1_rx_clk_2_int),
|
|
.rx_rst(qsfp_1_rx_rst_2_int),
|
|
.xgmii_txd(qsfp_1_txd_2_int),
|
|
.xgmii_txc(qsfp_1_txc_2_int),
|
|
.xgmii_rxd(qsfp_1_rxd_2_int),
|
|
.xgmii_rxc(qsfp_1_rxc_2_int),
|
|
.serdes_tx_data(qsfp_1_gt_txdata_2),
|
|
.serdes_tx_hdr(qsfp_1_gt_txheader_2),
|
|
.serdes_rx_data(qsfp_1_gt_rxdata_2),
|
|
.serdes_rx_hdr(qsfp_1_gt_rxheader_2),
|
|
.serdes_rx_bitslip(qsfp_1_gt_rxgearboxslip_2),
|
|
.rx_block_lock(qsfp_1_rx_block_lock_2),
|
|
.rx_high_ber()
|
|
);
|
|
|
|
assign qsfp_1_tx_clk_3_int = clk_156mhz_int;
|
|
assign qsfp_1_tx_rst_3_int = rst_156mhz_int;
|
|
|
|
assign qsfp_1_rx_clk_3_int = gt_rxusrclk[3];
|
|
|
|
sync_reset #(
|
|
.N(4)
|
|
)
|
|
qsfp_1_rx_rst_3_reset_sync_inst (
|
|
.clk(qsfp_1_rx_clk_3_int),
|
|
.rst(~gt_reset_rx_done),
|
|
.out(qsfp_1_rx_rst_3_int)
|
|
);
|
|
|
|
eth_phy_10g #(
|
|
.BIT_REVERSE(1)
|
|
)
|
|
qsfp_1_phy_3_inst (
|
|
.tx_clk(qsfp_1_tx_clk_3_int),
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.tx_rst(qsfp_1_tx_rst_3_int),
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.rx_clk(qsfp_1_rx_clk_3_int),
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.rx_rst(qsfp_1_rx_rst_3_int),
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.xgmii_txd(qsfp_1_txd_3_int),
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.xgmii_txc(qsfp_1_txc_3_int),
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.xgmii_rxd(qsfp_1_rxd_3_int),
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.xgmii_rxc(qsfp_1_rxc_3_int),
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.serdes_tx_data(qsfp_1_gt_txdata_3),
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.serdes_tx_hdr(qsfp_1_gt_txheader_3),
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|
.serdes_rx_data(qsfp_1_gt_rxdata_3),
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|
.serdes_rx_hdr(qsfp_1_gt_rxheader_3),
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|
.serdes_rx_bitslip(qsfp_1_gt_rxgearboxslip_3),
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.rx_block_lock(qsfp_1_rx_block_lock_3),
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|
.rx_high_ber()
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|
);
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|
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|
//assign led = sw[0] ? {qsfp_1_rx_block_lock_4, qsfp_1_rx_block_lock_3, qsfp_1_rx_block_lock_2, qsfp_1_rx_block_lock_1, qsfp_0_rx_block_lock_4, qsfp_0_rx_block_lock_3, qsfp_0_rx_block_lock_2, qsfp_0_rx_block_lock_1} : led_int;
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|
assign front_led = {1'b0, qsfp_0_rx_block_lock_0};
|
|
|
|
fpga_core
|
|
core_inst (
|
|
/*
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|
* Clock: 156.25 MHz
|
|
* Synchronous reset
|
|
*/
|
|
.clk(clk_156mhz_int),
|
|
.rst(rst_156mhz_int),
|
|
/*
|
|
* GPIO
|
|
*/
|
|
.user_led_g(user_led_g),
|
|
.user_led_r(user_led_r),
|
|
//.front_led(front_led),
|
|
.user_sw(user_sw_int),
|
|
|
|
/*
|
|
* Ethernet: QSFP28
|
|
*/
|
|
.qsfp_0_tx_clk_0(qsfp_0_tx_clk_0_int),
|
|
.qsfp_0_tx_rst_0(qsfp_0_tx_rst_0_int),
|
|
.qsfp_0_txd_0(qsfp_0_txd_0_int),
|
|
.qsfp_0_txc_0(qsfp_0_txc_0_int),
|
|
.qsfp_0_rx_clk_0(qsfp_0_rx_clk_0_int),
|
|
.qsfp_0_rx_rst_0(qsfp_0_rx_rst_0_int),
|
|
.qsfp_0_rxd_0(qsfp_0_rxd_0_int),
|
|
.qsfp_0_rxc_0(qsfp_0_rxc_0_int),
|
|
.qsfp_0_tx_clk_1(qsfp_0_tx_clk_1_int),
|
|
.qsfp_0_tx_rst_1(qsfp_0_tx_rst_1_int),
|
|
.qsfp_0_txd_1(qsfp_0_txd_1_int),
|
|
.qsfp_0_txc_1(qsfp_0_txc_1_int),
|
|
.qsfp_0_rx_clk_1(qsfp_0_rx_clk_1_int),
|
|
.qsfp_0_rx_rst_1(qsfp_0_rx_rst_1_int),
|
|
.qsfp_0_rxd_1(qsfp_0_rxd_1_int),
|
|
.qsfp_0_rxc_1(qsfp_0_rxc_1_int),
|
|
.qsfp_0_tx_clk_2(qsfp_0_tx_clk_2_int),
|
|
.qsfp_0_tx_rst_2(qsfp_0_tx_rst_2_int),
|
|
.qsfp_0_txd_2(qsfp_0_txd_2_int),
|
|
.qsfp_0_txc_2(qsfp_0_txc_2_int),
|
|
.qsfp_0_rx_clk_2(qsfp_0_rx_clk_2_int),
|
|
.qsfp_0_rx_rst_2(qsfp_0_rx_rst_2_int),
|
|
.qsfp_0_rxd_2(qsfp_0_rxd_2_int),
|
|
.qsfp_0_rxc_2(qsfp_0_rxc_2_int),
|
|
.qsfp_0_tx_clk_3(qsfp_0_tx_clk_3_int),
|
|
.qsfp_0_tx_rst_3(qsfp_0_tx_rst_3_int),
|
|
.qsfp_0_txd_3(qsfp_0_txd_3_int),
|
|
.qsfp_0_txc_3(qsfp_0_txc_3_int),
|
|
.qsfp_0_rx_clk_3(qsfp_0_rx_clk_3_int),
|
|
.qsfp_0_rx_rst_3(qsfp_0_rx_rst_3_int),
|
|
.qsfp_0_rxd_3(qsfp_0_rxd_3_int),
|
|
.qsfp_0_rxc_3(qsfp_0_rxc_3_int),
|
|
.qsfp_1_tx_clk_0(qsfp_1_tx_clk_0_int),
|
|
.qsfp_1_tx_rst_0(qsfp_1_tx_rst_0_int),
|
|
.qsfp_1_txd_0(qsfp_1_txd_0_int),
|
|
.qsfp_1_txc_0(qsfp_1_txc_0_int),
|
|
.qsfp_1_rx_clk_0(qsfp_1_rx_clk_0_int),
|
|
.qsfp_1_rx_rst_0(qsfp_1_rx_rst_0_int),
|
|
.qsfp_1_rxd_0(qsfp_1_rxd_0_int),
|
|
.qsfp_1_rxc_0(qsfp_1_rxc_0_int),
|
|
.qsfp_1_tx_clk_1(qsfp_1_tx_clk_1_int),
|
|
.qsfp_1_tx_rst_1(qsfp_1_tx_rst_1_int),
|
|
.qsfp_1_txd_1(qsfp_1_txd_1_int),
|
|
.qsfp_1_txc_1(qsfp_1_txc_1_int),
|
|
.qsfp_1_rx_clk_1(qsfp_1_rx_clk_1_int),
|
|
.qsfp_1_rx_rst_1(qsfp_1_rx_rst_1_int),
|
|
.qsfp_1_rxd_1(qsfp_1_rxd_1_int),
|
|
.qsfp_1_rxc_1(qsfp_1_rxc_1_int),
|
|
.qsfp_1_tx_clk_2(qsfp_1_tx_clk_2_int),
|
|
.qsfp_1_tx_rst_2(qsfp_1_tx_rst_2_int),
|
|
.qsfp_1_txd_2(qsfp_1_txd_2_int),
|
|
.qsfp_1_txc_2(qsfp_1_txc_2_int),
|
|
.qsfp_1_rx_clk_2(qsfp_1_rx_clk_2_int),
|
|
.qsfp_1_rx_rst_2(qsfp_1_rx_rst_2_int),
|
|
.qsfp_1_rxd_2(qsfp_1_rxd_2_int),
|
|
.qsfp_1_rxc_2(qsfp_1_rxc_2_int),
|
|
.qsfp_1_tx_clk_3(qsfp_1_tx_clk_3_int),
|
|
.qsfp_1_tx_rst_3(qsfp_1_tx_rst_3_int),
|
|
.qsfp_1_txd_3(qsfp_1_txd_3_int),
|
|
.qsfp_1_txc_3(qsfp_1_txc_3_int),
|
|
.qsfp_1_rx_clk_3(qsfp_1_rx_clk_3_int),
|
|
.qsfp_1_rx_rst_3(qsfp_1_rx_rst_3_int),
|
|
.qsfp_1_rxd_3(qsfp_1_rxd_3_int),
|
|
.qsfp_1_rxc_3(qsfp_1_rxc_3_int)
|
|
);
|
|
|
|
endmodule
|