FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-28 07:03:08 +08:00
Code Issues Projects Releases Wiki Activity
verilog-ethernet/example/Arty/fpga/rtl
History
Alex Forencich 27ed447005 Use common sync_reset module files
2020-03-27 18:27:45 -07:00
..
debounce_switch.v
Add Arty example design
2019-03-28 19:38:55 -07:00
fpga_core.v
Fix typo
2019-07-19 10:29:55 -07:00
fpga.v
Use common sync_reset module files
2020-03-27 18:27:45 -07:00
sync_signal.v
Add Arty example design
2019-03-28 19:38:55 -07:00