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verilog-ethernet/example/Alveo/fpga_25g/rtl
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Alex Forencich 3535e53746 Add example design for Alveo U55C and Alveo U55N/Varium C1100 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-11-10 15:40:14 -08:00
..
debounce_switch.v
Rename AU200 to Alveo
2023-11-08 11:50:50 -08:00
eth_xcvr_phy_quad_wrapper.v
Rename AU200 to Alveo
2023-11-08 11:50:50 -08:00
eth_xcvr_phy_wrapper.v
Rename AU200 to Alveo
2023-11-08 11:50:50 -08:00
fpga_au50.v
Merge AU50 into Alveo example design
2023-11-10 15:32:38 -08:00
fpga_au55.v
Add example design for Alveo U55C and Alveo U55N/Varium C1100
2023-11-10 15:40:14 -08:00
fpga_au200.v
Rework Alveo parametrization
2023-11-10 15:25:38 -08:00
fpga_au280.v
Merge AU280 into Alveo example design
2023-11-10 15:30:37 -08:00
fpga_core.v
Rework Alveo parametrization
2023-11-10 15:25:38 -08:00
sync_signal.v
Rename AU200 to Alveo
2023-11-08 11:50:50 -08:00