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verilog-ethernet/syn/quartus
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Alex Forencich 7751aba8da Reorganize timing constraints
2021-05-18 16:15:41 -07:00
..
eth_mac_1g_gmii.sdc
Reorganize timing constraints
2021-05-18 16:15:41 -07:00
eth_mac_1g_rgmii.sdc
Reorganize timing constraints
2021-05-18 16:15:41 -07:00
gmii_phy_if.sdc
Reorganize timing constraints
2021-05-18 16:15:41 -07:00
mii_phy_if.sdc
Reorganize timing constraints
2021-05-18 16:15:41 -07:00
rgmii_io.sdc
Reorganize timing constraints
2021-05-18 16:15:41 -07:00
rgmii_phy_if.sdc
Reorganize timing constraints
2021-05-18 16:15:41 -07:00