mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-14 06:43:18 +08:00
35 lines
1.7 KiB
Tcl
35 lines
1.7 KiB
Tcl
# Copyright (c) 2020 Alex Forencich
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#
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# Permission is hereby granted, free of charge, to any person obtaining a copy
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# of this software and associated documentation files (the "Software"), to deal
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# in the Software without restriction, including without limitation the rights
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# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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# copies of the Software, and to permit persons to whom the Software is
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# furnished to do so, subject to the following conditions:
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#
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# The above copyright notice and this permission notice shall be included in
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# all copies or substantial portions of the Software.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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# THE SOFTWARE.
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# GMII Gigabit Ethernet MAC timing constraints
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proc constrain_eth_mac_1g_gmii_inst { inst } {
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puts "Inserting timing constraints for eth_mac_1g_gmii instance $inst"
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# MII select sync
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set_max_delay -from [get_registers "$inst|mii_select_reg"] -to [get_registers "$inst|tx_mii_select_sync[0]"] 8.000
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set_max_delay -from [get_registers "$inst|mii_select_reg"] -to [get_registers "$inst|rx_mii_select_sync[0]"] 8.000
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# RX prescale sync
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set_max_delay -from [get_registers "$inst|rx_prescale[2]"] -to [get_registers "$inst|rx_prescale_sync[0]"] 8.000
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constrain_gmii_phy_if_inst "$inst|gmii_phy_if_inst"
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}
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