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verilog-ethernet
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Alex Forencich
bd8e8e5b20
Add PTP time distribution components
...
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-11-07 13:07:15 -08:00
..
eth_mac_1g_gmii.tcl
Update TCL timing constraints to handle clocks from OOC IP that are not constrained during synthesis
2023-07-26 14:59:19 -07:00
eth_mac_1g_rgmii.tcl
Update TCL timing constraints to handle clocks from OOC IP that are not constrained during synthesis
2023-07-26 14:59:19 -07:00
eth_mac_fifo.tcl
Update TCL timing constraints to handle clocks from OOC IP that are not constrained during synthesis
2023-07-26 14:59:19 -07:00
eth_mac.tcl
Update TCL timing constraints to handle clocks from OOC IP that are not constrained during synthesis
2023-07-26 14:59:19 -07:00
gmii_phy_if.tcl
Reorganize timing constraints
2021-05-18 16:15:41 -07:00
mii_phy_if.tcl
Reorganize timing constraints
2021-05-18 16:15:41 -07:00
ptp_clock_cdc.tcl
Use phase detector in PTP CDC module for coarse period tuning, use 9 LSBs of timestamp for fine sync to avoid rollover corrections, reduce FNS comparison width to 4 bits
2023-09-23 14:58:44 -07:00
ptp_td_leaf.tcl
Add PTP time distribution components
2023-11-07 13:07:15 -08:00
rgmii_phy_if.tcl
Update TCL timing constraints to handle clocks from OOC IP that are not constrained during synthesis
2023-07-26 14:59:19 -07:00
