mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-28 07:03:08 +08:00
22 lines
1015 B
Tcl
22 lines
1015 B
Tcl
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create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name gtwizard_ultrascale_0
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set_property -dict [list CONFIG.preset {GTY-10GBASE-R}] [get_ips gtwizard_ultrascale_0]
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set_property -dict [list \
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CONFIG.CHANNEL_ENABLE {X1Y51 X1Y50 X1Y49 X1Y48 X1Y47 X1Y46 X1Y45 X1Y44} \
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CONFIG.TX_MASTER_CHANNEL {X1Y48} \
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CONFIG.RX_MASTER_CHANNEL {X1Y48} \
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CONFIG.TX_LINE_RATE {10.3125} \
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CONFIG.TX_REFCLK_FREQUENCY {161.1328125} \
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CONFIG.TX_USER_DATA_WIDTH {64} \
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CONFIG.TX_INT_DATA_WIDTH {64} \
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CONFIG.RX_LINE_RATE {10.3125} \
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CONFIG.RX_REFCLK_FREQUENCY {161.1328125} \
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CONFIG.RX_USER_DATA_WIDTH {64} \
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CONFIG.RX_INT_DATA_WIDTH {64} \
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CONFIG.RX_REFCLK_SOURCE {X1Y51 clk1 X1Y50 clk1 X1Y49 clk1 X1Y48 clk1 X1Y47 clk1+1 X1Y46 clk1+1 X1Y45 clk1+1 X1Y44 clk1+1} \
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CONFIG.TX_REFCLK_SOURCE {X1Y51 clk1 X1Y50 clk1 X1Y49 clk1 X1Y48 clk1 X1Y47 clk1+1 X1Y46 clk1+1 X1Y45 clk1+1 X1Y44 clk1+1} \
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CONFIG.FREERUN_FREQUENCY {125} \
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] [get_ips gtwizard_ultrascale_0]
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