verilog-ethernet/fpga at bfc97ac311c0ffb9e757b319645e507925d85c5e - verilog-ethernet - Gitea: Git with a cup of tea

FPGA/verilog-ethernet

mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-28 07:03:08 +08:00

History

Alex Forencich 6b23d83361 Set FIFO size in example design

2015-05-08 01:45:42 -07:00

..

Add example design for Digilent Atlys board

2015-02-28 20:05:05 -08:00

Add example design for Digilent Atlys board

2015-02-28 20:05:05 -08:00

Update example design to use FIFO wrapper

2015-05-08 00:45:27 -07:00

Add example design for Digilent Atlys board

2015-02-28 20:05:05 -08:00

Set FIFO size in example design

2015-05-08 01:45:42 -07:00

Update example design to use FIFO wrapper

2015-05-08 00:45:27 -07:00

clock.ucf

Add example design for Digilent Atlys board

2015-02-28 20:05:05 -08:00

fpga.ucf

Add example design for Digilent Atlys board

2015-02-28 20:05:05 -08:00

Makefile

Add example design for Digilent Atlys board

2015-02-28 20:05:05 -08:00