verilog-ethernet/example at c2e459c97129106f2ef22e8303946a39625747f5 - verilog-ethernet - Gitea: Git with a cup of tea

FPGA/verilog-ethernet

mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-14 06:43:18 +08:00

History

Alex Forencich c2e459c971 Connect transceiver control lines

2017-03-09 17:14:14 -08:00

..

Update UDP modules and example designs to utilize UDP checksum modules

2016-09-30 22:15:21 -07:00

Connect transceiver control lines

2017-03-09 17:14:14 -08:00

Update UDP modules and example designs to utilize UDP checksum modules

2016-09-30 22:15:21 -07:00

NexysVideo/fpga

Fix Vivado clock groups

2016-10-06 17:52:23 -07:00

Fix Vivado clock groups

2016-10-06 17:52:23 -07:00