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verilog-ethernet/example/HTG9200/fpga_25g/ip
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Alex Forencich d3fb11b2c3 Use unified 10G/25G design for HTG9200 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-07-13 21:35:42 -07:00
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eth_xcvr_gt.tcl
Use unified 10G/25G design for HTG9200
2023-07-13 21:35:42 -07:00