FPGA/verilog-ethernet
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verilog-ethernet/example/KC705/fpga_gmii/rtl
History
Alex Forencich c5e886769a Fix typo
2019-07-19 10:29:55 -07:00
..
debounce_switch.v
Add KC705 GMII example design
2019-05-02 19:29:47 -07:00
fpga_core.v
Fix typo
2019-07-19 10:29:55 -07:00
fpga.v
Fix signal name
2019-05-02 20:30:37 -07:00
sync_reset.v
Add KC705 GMII example design
2019-05-02 19:29:47 -07:00
sync_signal.v
Add KC705 GMII example design
2019-05-02 19:29:47 -07:00