FPGA/verilog-ethernet
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verilog-ethernet/rtl
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Alex Forencich d2df971fc9 Add AXI stream frame length measurement module and testbenches
2019-03-07 22:57:46 -08:00
..
arbiter.v
Happy new year
2018-02-26 12:25:20 -08:00
axis_adapter.v
Change cycle to segment
2018-12-03 12:40:06 -08:00
axis_arb_mux_wrap.py
Add wrapper generators
2018-10-25 14:23:00 -07:00
axis_arb_mux.v
Bitwise operators instead of generate
2018-12-09 00:03:09 -08:00
axis_async_fifo.v
Fix frame FIFO full logic bug
2018-12-09 00:01:38 -08:00
axis_broadcast.v
Add AXI stream broadcast module and testbench
2019-02-27 19:46:30 -08:00
axis_cobs_decode.v
Update FIFO instance, rename ports
2018-10-25 10:17:58 -07:00
axis_cobs_encode.v
Update FIFO instantiations
2018-10-25 16:06:32 -07:00
axis_crosspoint_wrap.py
Add wrapper generators
2018-10-25 14:23:00 -07:00
axis_crosspoint.v
Convert generated crosspoint to verilog parametrized crosspoint
2018-10-24 13:44:39 -07:00
axis_demux_wrap.py
Add wrapper generators
2018-10-25 14:23:00 -07:00
axis_demux.v
Match width
2018-12-09 00:04:30 -08:00
axis_fifo.v
Fix frame FIFO full logic bug
2018-12-09 00:01:38 -08:00
axis_frame_join_wrap.py
Add wrapper generators
2018-10-25 14:23:00 -07:00
axis_frame_join.v
Update parameter ordering
2018-10-25 10:20:17 -07:00
axis_frame_len.v
Add AXI stream frame length measurement module and testbenches
2019-03-07 22:57:46 -08:00
axis_frame_length_adjust_fifo.v
Update FIFO instantiations
2018-10-25 16:06:32 -07:00
axis_frame_length_adjust.v
Update FIFO instance, rename ports
2018-10-25 10:15:16 -07:00
axis_ll_bridge.v
Rename ports
2018-10-25 11:19:28 -07:00
axis_mux_wrap.py
Add wrapper generators
2018-10-25 14:23:00 -07:00
axis_mux.v
Use logical operator instead of bitwise
2018-12-09 00:04:56 -08:00
axis_pipeline_register.v
Fix generate statement
2018-11-28 14:18:09 -08:00
axis_rate_limit.v
Rename ports
2018-10-25 11:30:35 -07:00
axis_register.v
Use logical operators
2018-10-24 22:24:27 -07:00
axis_srl_fifo.v
Rename ports
2018-10-25 11:52:08 -07:00
axis_srl_register.v
Rename ports
2018-10-25 11:56:52 -07:00
axis_stat_counter.v
Rename ports
2018-10-25 11:59:13 -07:00
axis_switch.v
Connect arbiter parameters to top level
2018-10-24 21:09:00 -07:00
axis_tap.v
Rename ports
2018-10-25 12:00:34 -07:00
ll_axis_bridge.v
Rename ports
2018-10-25 11:19:28 -07:00
priority_encoder.v
Happy new year
2018-02-26 12:25:20 -08:00