FPGA/verilog-ethernet
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verilog-ethernet/example/Alveo
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Alex Forencich 3535e53746 Add example design for Alveo U55C and Alveo U55N/Varium C1100 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-11-10 15:40:14 -08:00
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fpga_25g
Add example design for Alveo U55C and Alveo U55N/Varium C1100
2023-11-10 15:40:14 -08:00