FPGA/verilog-ethernet
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verilog-ethernet/example/Arista_7132LB/fpga_25g/ip
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Alex Forencich 68736d02ae Add 10G/25G design for Arista 7132LB-48Y4C switch 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-08-25 23:06:49 -07:00
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eth_xcvr_gt.tcl
Add 10G/25G design for Arista 7132LB-48Y4C switch
2023-08-25 23:06:49 -07:00