FPGA/verilog-ethernet
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verilog-ethernet/example/Arista_7132LB/fpga_25g/rtl
History
Alex Forencich 0986d1e901 Rework 7132 parametrization 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-11-08 13:36:21 -08:00
..
eth_xcvr_phy_quad_wrapper.v
Add 10G/25G design for Arista 7132LB-48Y4C switch
2023-08-25 23:06:49 -07:00
eth_xcvr_phy_wrapper.v
Add 10G/25G design for Arista 7132LB-48Y4C switch
2023-08-25 23:06:49 -07:00
fpga_core.v
Rework 7132 parametrization
2023-11-08 13:36:21 -08:00
fpga.v
Rework 7132 parametrization
2023-11-08 13:36:21 -08:00
sync_signal.v
Add 10G/25G design for Arista 7132LB-48Y4C switch
2023-08-25 23:06:49 -07:00