FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-02-04 07:13:13 +08:00
Code Issues Projects Releases Wiki Activity
verilog-ethernet/tb/eth_mac_1g
History
Alex Forencich 009560f583 Use latest version of cocotbext-eth 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-11-07 12:18:46 -08:00
..
Makefile
Add MAC control layer to core 1G and 10G MAC modules
2023-07-23 22:24:42 -07:00
test_eth_mac_1g.py
Use latest version of cocotbext-eth
2023-11-07 12:18:46 -08:00