mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-02-04 07:13:13 +08:00
23 lines
896 B
Tcl
23 lines
896 B
Tcl
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create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name gtwizard_ultrascale_0
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set_property -dict [list CONFIG.preset {GTH-10GBASE-R}] [get_ips gtwizard_ultrascale_0]
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set_property -dict [list \
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CONFIG.CHANNEL_ENABLE {X0Y13 X0Y12} \
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CONFIG.TX_MASTER_CHANNEL {X0Y12} \
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CONFIG.RX_MASTER_CHANNEL {X0Y12} \
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CONFIG.TX_LINE_RATE {10.3125} \
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CONFIG.TX_REFCLK_FREQUENCY {161.1328125} \
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CONFIG.TX_USER_DATA_WIDTH {64} \
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CONFIG.TX_INT_DATA_WIDTH {32} \
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CONFIG.RX_LINE_RATE {10.3125} \
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CONFIG.RX_REFCLK_FREQUENCY {161.1328125} \
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CONFIG.RX_USER_DATA_WIDTH {64} \
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CONFIG.RX_INT_DATA_WIDTH {32} \
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CONFIG.RX_REFCLK_SOURCE {X0Y13 clk0 X0Y12 clk0} \
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CONFIG.TX_REFCLK_SOURCE {X0Y13 clk0 X0Y12 clk0} \
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CONFIG.FREERUN_FREQUENCY {125} \
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CONFIG.ENABLE_OPTIONAL_PORTS {rxpolarity_in txpolarity_in} \
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] [get_ips gtwizard_ultrascale_0]
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