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verilog-ethernet
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Alex Forencich
274831c268
Fix PTP clock CDC module timing constraints
...
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-05-05 21:41:41 -07:00
..
eth_mac_1g_gmii.tcl
Reorganize timing constraints
2021-05-18 16:15:41 -07:00
eth_mac_1g_rgmii.tcl
Reorganize timing constraints
2021-05-18 16:15:41 -07:00
eth_mac_fifo.tcl
Reorganize timing constraints
2021-05-18 16:15:41 -07:00
gmii_phy_if.tcl
Reorganize timing constraints
2021-05-18 16:15:41 -07:00
mii_phy_if.tcl
Reorganize timing constraints
2021-05-18 16:15:41 -07:00
ptp_clock_cdc.tcl
Fix PTP clock CDC module timing constraints
2022-05-05 21:41:41 -07:00
rgmii_phy_if.tcl
Reorganize timing constraints
2021-05-18 16:15:41 -07:00