mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-14 06:43:18 +08:00
679 lines
29 KiB
Python
679 lines
29 KiB
Python
"""
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Copyright (c) 2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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from myhdl import *
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import xgmii_ep
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ETH_PRE = 0x55
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ETH_SFD = 0xD5
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XGMII_IDLE = 0x07
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XGMII_LPI = 0x06
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XGMII_START = 0xfb
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XGMII_TERM = 0xfd
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XGMII_ERROR = 0xfe
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XGMII_SEQ_OS = 0x9c
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XGMII_RES_0 = 0x1c
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XGMII_RES_1 = 0x3c
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XGMII_RES_2 = 0x7c
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XGMII_RES_3 = 0xbc
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XGMII_RES_4 = 0xdc
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XGMII_RES_5 = 0xf7
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XGMII_SIG_OS = 0x5c
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CTRL_IDLE = 0x00
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CTRL_LPI = 0x06
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CTRL_ERROR = 0x1e
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CTRL_RES_0 = 0x2d
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CTRL_RES_1 = 0x33
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CTRL_RES_2 = 0x4b
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CTRL_RES_3 = 0x55
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CTRL_RES_4 = 0x66
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CTRL_RES_5 = 0x78
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O_SEQ_OS = 0x0
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O_SIG_OS = 0xf
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SYNC_DATA = 0b10
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SYNC_CTRL = 0b01
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BLOCK_TYPE_CTRL = 0x1e # C7 C6 C5 C4 C3 C2 C1 C0 BT
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BLOCK_TYPE_OS_4 = 0x2d # D7 D6 D5 O4 C3 C2 C1 C0 BT
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BLOCK_TYPE_START_4 = 0x33 # D7 D6 D5 C3 C2 C1 C0 BT
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BLOCK_TYPE_OS_START = 0x66 # D7 D6 D5 O0 D3 D2 D1 BT
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BLOCK_TYPE_OS_04 = 0x55 # D7 D6 D5 O4 O0 D3 D2 D1 BT
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BLOCK_TYPE_START_0 = 0x78 # D7 D6 D5 D4 D3 D2 D1 BT
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BLOCK_TYPE_OS_0 = 0x4b # C7 C6 C5 C4 O0 D3 D2 D1 BT
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BLOCK_TYPE_TERM_0 = 0x87 # C7 C6 C5 C4 C3 C2 C1 BT
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BLOCK_TYPE_TERM_1 = 0x99 # C7 C6 C5 C4 C3 C2 D0 BT
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BLOCK_TYPE_TERM_2 = 0xaa # C7 C6 C5 C4 C3 D1 D0 BT
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BLOCK_TYPE_TERM_3 = 0xb4 # C7 C6 C5 C4 D2 D1 D0 BT
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BLOCK_TYPE_TERM_4 = 0xcc # C7 C6 C5 D3 D2 D1 D0 BT
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BLOCK_TYPE_TERM_5 = 0xd2 # C7 C6 D4 D3 D2 D1 D0 BT
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BLOCK_TYPE_TERM_6 = 0xe1 # C7 D5 D4 D3 D2 D1 D0 BT
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BLOCK_TYPE_TERM_7 = 0xff # D6 D5 D4 D3 D2 D1 D0 BT
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def block_type_term_lane(bt):
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if bt == BLOCK_TYPE_TERM_0:
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return 0
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elif bt == BLOCK_TYPE_TERM_1:
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return 1
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elif bt == BLOCK_TYPE_TERM_2:
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return 2
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elif bt == BLOCK_TYPE_TERM_3:
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return 3
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elif bt == BLOCK_TYPE_TERM_4:
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return 4
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elif bt == BLOCK_TYPE_TERM_5:
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return 5
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elif bt == BLOCK_TYPE_TERM_6:
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return 6
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elif bt == BLOCK_TYPE_TERM_7:
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return 7
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else:
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return None
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class BaseRSerdesSource(object):
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def __init__(self, ifg=12, enable_dic=True):
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self.has_logic = False
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self.queue = []
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self.ifg = ifg
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self.enable_dic = enable_dic
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self.force_offset_start = False
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def send(self, frame):
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self.queue.append(xgmii_ep.XGMIIFrame(frame))
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def count(self):
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return len(self.queue)
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def empty(self):
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return not self.queue
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def create_logic(self,
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clk,
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tx_data,
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tx_header,
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enable=True,
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scramble=True,
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reverse=False,
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name=None
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):
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assert not self.has_logic
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self.has_logic = True
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assert len(tx_data) in [64]
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assert len(tx_data) == len(tx_header)*32
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bw = int(len(tx_data)/8)
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@instance
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def logic():
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frame = None
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ccl = []
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ifg_cnt = 0
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deficit_idle_cnt = 0
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scrambler_state = 0
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while True:
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yield clk.posedge
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if enable:
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data = 0x000000000000001e
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header = 0b01
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if ifg_cnt > bw-1 or (not self.enable_dic and ifg_cnt > 0):
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ifg_cnt = max(ifg_cnt - bw, 0)
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elif ccl:
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header, data = ccl.pop(0)
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if not ccl:
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l = block_type_term_lane(data & 0xff)
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if l is not None:
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ifg_cnt = self.ifg - (bw-l) + deficit_idle_cnt
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else:
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ifg_cnt = self.ifg + deficit_idle_cnt
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elif self.queue:
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frame = self.queue.pop(0)
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dl, cl = frame.build()
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if name is not None:
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print("[%s] Sending frame %s" % (name, repr(frame)))
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assert len(dl) > 0
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assert dl[0] == ETH_PRE
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dl[0] = XGMII_START
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cl[0] = 1
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dl.append(XGMII_TERM)
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cl.append(1)
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if (bw == 8 and ifg_cnt >= 4) or self.force_offset_start:
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ifg_cnt = max(ifg_cnt-4, 0)
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dl = [XGMII_IDLE]*4+dl
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cl = [1]*4+cl
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deficit_idle_cnt = max(ifg_cnt, 0)
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ifg_cnt = 0
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# pad length to multiple of 8 by adding idles
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if len(dl)%8:
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for k in range(8-(len(dl)%8)):
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dl.append(XGMII_IDLE)
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cl.append(1)
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# 10GBASE-R encoding
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for k in range(0, len(dl), 8):
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di = dl[k:k+8]
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ci = cl[k:k+8]
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# remap control characters
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ctrl = 0
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ctrl_decode_error = [0]*8
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for i in range(8):
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if not ci[i]:
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# data
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ctrl |= CTRL_ERROR << i*7
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elif di[i] == XGMII_IDLE:
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# idle
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ctrl |= CTRL_IDLE << i*7
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elif di[i] == XGMII_LPI:
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# LPI
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ctrl |= CTRL_LPI << i*7
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elif di[i] == XGMII_ERROR:
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# error
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ctrl |= CTRL_ERROR << i*7
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elif di[i] == XGMII_RES_0:
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# reserved0
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ctrl |= CTRL_RES_0 << i*7
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elif di[i] == XGMII_RES_1:
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# reserved1
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ctrl |= CTRL_RES_1 << i*7
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elif di[i] == XGMII_RES_2:
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# reserved2
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ctrl |= CTRL_RES_2 << i*7
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elif di[i] == XGMII_RES_3:
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# reserved3
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ctrl |= CTRL_RES_3 << i*7
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elif di[i] == XGMII_RES_4:
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# reserved4
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ctrl |= CTRL_RES_4 << i*7
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elif di[i] == XGMII_RES_5:
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# reserved5
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ctrl |= CTRL_RES_5 << i*7
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else:
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# invalid
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ctrl |= CTRL_ERROR << i*7
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ctrl_decode_error[i] = ci[i]
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if not any(ci):
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# data
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h = SYNC_DATA
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d = 0
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for i in range(8):
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d |= di[i] << i*8
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else:
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# control
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h = SYNC_CTRL
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if ci[0] and di[0] == XGMII_START and not any(ci[1:]):
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# start in lane 0
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d = BLOCK_TYPE_START_0
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for i in range(1,8):
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d |= di[i] << i*8
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elif ci[4] and di[4] == XGMII_START and not any(ci[5:]):
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# start in lane 4
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if ci[0] and (di[0] == XGMII_SEQ_OS or di[0] == XGMII_SIG_OS) and not any(ci[1:4]):
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# ordered set in lane 0
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d = BLOCK_TYPE_OS_START
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for i in range(1,4):
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d |= di[i] << i*8
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if di[0] == XGMII_SIG_OS:
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# signal ordered set
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d |= O_SIG_OS << 32
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else:
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# other control
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d = BLOCK_TYPE_START_4 | (ctrl & 0xfffffff) << 8
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for i in range(5,8):
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d |= di[i] << i*8
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elif ci[0] and (di[0] == XGMII_SEQ_OS or di[0] == XGMII_SIG_OS) and not any(ci[1:4]):
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# ordered set in lane 0
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if ci[4] and (di[4] == XGMII_SEQ_OS or di[4] == XGMII_SIG_OS) and not any(ci[5:8]):
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# ordered set in lane 4
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d = BLOCK_TYPE_OS_04
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for i in range(5,8):
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d |= di[i] << i*8
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if di[4] == XGMII_SIG_OS:
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# signal ordered set
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d |= O_SIG_OS << 36
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else:
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d = BLOCK_TYPE_OS_0 | (ctrl & 0xfffffff) << 40
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for i in range(1,4):
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d |= di[i] << i*8
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if di[0] == XGMII_SIG_OS:
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# signal ordered set
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d |= O_SIG_OS << 32
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elif ci[4] and (di[4] == XGMII_SEQ_OS or di[4] == XGMII_SIG_OS) and not any(ci[5:8]):
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# ordered set in lane 4
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d = BLOCK_TYPE_OS_4 | (ctrl & 0xfffffff) << 8
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for i in range(5,8):
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d |= di[i] << i*8
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if di[4] == XGMII_SIG_OS:
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# signal ordered set
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d |= O_SIG_OS << 36
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elif ci[0] and di[0] == XGMII_TERM:
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# terminate in lane 0
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d = BLOCK_TYPE_TERM_0 | (ctrl & 0xffffffffffff80) << 8
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elif ci[1] and di[1] == XGMII_TERM and not ci[0]:
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# terminate in lane 1
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d = BLOCK_TYPE_TERM_1 | (ctrl & 0xffffffffffc000) << 8 | di[0] << 8
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elif ci[2] and di[2] == XGMII_TERM and not any(ci[0:2]):
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# terminate in lane 2
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d = BLOCK_TYPE_TERM_2 | (ctrl & 0xffffffffe00000) << 8
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for i in range(2):
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d |= di[i] << ((i+1)*8)
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elif ci[3] and di[3] == XGMII_TERM and not any(ci[0:3]):
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# terminate in lane 3
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d = BLOCK_TYPE_TERM_3 | (ctrl & 0xfffffff0000000) << 8
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for i in range(3):
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d |= di[i] << ((i+1)*8)
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elif ci[4] and di[4] == XGMII_TERM and not any(ci[0:4]):
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# terminate in lane 4
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d = BLOCK_TYPE_TERM_4 | (ctrl & 0xfffff800000000) << 8
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for i in range(4):
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d |= di[i] << ((i+1)*8)
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elif ci[5] and di[5] == XGMII_TERM and not any(ci[0:5]):
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# terminate in lane 5
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d = BLOCK_TYPE_TERM_5 | (ctrl & 0xfffc0000000000) << 8
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for i in range(5):
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d |= di[i] << ((i+1)*8)
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elif ci[6] and di[6] == XGMII_TERM and not any(ci[0:6]):
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# terminate in lane 6
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d = BLOCK_TYPE_TERM_6 | (ctrl & 0xfe000000000000) << 8
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for i in range(6):
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d |= di[i] << ((i+1)*8)
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elif ci[7] and di[7] == XGMII_TERM and not any(ci[0:7]):
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# terminate in lane 7
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d = BLOCK_TYPE_TERM_7
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for i in range(7):
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d |= di[i] << ((i+1)*8)
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else:
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# all control
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d = BLOCK_TYPE_CTRL | ctrl << 8
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ccl.append((h, d))
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header, data = ccl.pop(0)
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if not ccl:
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l = block_type_term_lane(data & 0xff)
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if l is not None:
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ifg_cnt = self.ifg - (bw-l) + deficit_idle_cnt
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else:
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ifg_cnt = self.ifg + deficit_idle_cnt
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else:
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ifg_cnt = 0
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deficit_idle_cnt = 0
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if scramble:
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# 64b66b scrambler
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b = 0
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for i in range(len(tx_data)):
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if bool(scrambler_state & (1<<38)) ^ bool(scrambler_state & (1<<57)) ^ bool(data & (1 << i)):
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scrambler_state = ((scrambler_state & 0x1ffffffffffffff) << 1) | 1
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b = b | (1 << i)
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else:
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scrambler_state = (scrambler_state & 0x1ffffffffffffff) << 1
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data = b
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if reverse:
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# bit reverse
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data = sum(1 << (63-i) for i in range(64) if (data >> i) & 1)
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header = sum(1 << (1-i) for i in range(2) if (header >> i) & 1)
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tx_data.next = data
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tx_header.next = header
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return instances()
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class BaseRSerdesSink(object):
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def __init__(self):
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self.has_logic = False
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self.queue = []
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self.sync = Signal(intbv(0))
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def recv(self):
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if self.queue:
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return self.queue.pop(0)
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return None
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def count(self):
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return len(self.queue)
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def empty(self):
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return not self.queue
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def wait(self, timeout=0):
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yield delay(0)
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if self.queue:
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return
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if timeout:
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yield self.sync, delay(timeout)
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else:
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yield self.sync
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def create_logic(self,
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clk,
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rx_data,
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rx_header,
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enable=True,
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scramble=True,
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reverse=False,
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name=None
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):
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assert not self.has_logic
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self.has_logic = True
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assert len(rx_data) in [64]
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assert len(rx_data) == len(rx_header)*32
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bw = int(len(rx_data)/8)
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@instance
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def logic():
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frame = None
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d = []
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c = []
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scrambler_state = 0
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while True:
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yield clk.posedge
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if enable:
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data = int(rx_data)
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header = int(rx_header)
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if reverse:
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# bit reverse
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data = sum(1 << (63-i) for i in range(64) if (data >> i) & 1)
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header = sum(1 << (1-i) for i in range(2) if (header >> i) & 1)
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if scramble:
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# 64b66b descrambler
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b = 0
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for i in range(len(rx_data)):
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if bool(scrambler_state & (1<<38)) ^ bool(scrambler_state & (1<<57)) ^ bool(data & (1 << i)):
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b = b | (1 << i)
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scrambler_state = (scrambler_state & 0x1ffffffffffffff) << 1 | bool(data & (1 << i))
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data = b
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# 10GBASE-R decoding
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# remap control characters
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ctrl = [0]*8
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for i in range(8):
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if (data >> i*7+8) & 0x7f == CTRL_IDLE:
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# idle
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ctrl[i] = XGMII_IDLE;
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elif (data >> i*7+8) & 0x7f == CTRL_LPI:
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# LPI
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ctrl[i] = XGMII_LPI
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elif (data >> i*7+8) & 0x7f == CTRL_ERROR:
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# error
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ctrl[i] = XGMII_ERROR
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elif (data >> i*7+8) & 0x7f == CTRL_RES_0:
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# reserved0
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ctrl[i] = XGMII_RES_0
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elif (data >> i*7+8) & 0x7f == CTRL_RES_1:
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# reserved1
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ctrl[i] = XGMII_RES_1
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elif (data >> i*7+8) & 0x7f == CTRL_RES_2:
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# reserved2
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ctrl[i] = XGMII_RES_2
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elif (data >> i*7+8) & 0x7f == CTRL_RES_3:
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# reserved3
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ctrl[i] = XGMII_RES_3
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elif (data >> i*7+8) & 0x7f == CTRL_RES_4:
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# reserved4
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ctrl[i] = XGMII_RES_4
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elif (data >> i*7+8) & 0x7f == CTRL_RES_5:
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# reserved5
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ctrl[i] = XGMII_RES_5
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else:
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# invalid
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ctrl[i] = XGMII_ERROR
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dl = []
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cl = []
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if header == SYNC_DATA:
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# data
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for k in range(8):
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dl.append((data >> k*8) & 0xff)
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cl.append(0)
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elif header == SYNC_CTRL:
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if data & 0xff == BLOCK_TYPE_CTRL:
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# C7 C6 C5 C4 C3 C2 C1 C0 BT
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dl = ctrl
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cl = [1]*8
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elif data & 0xff == BLOCK_TYPE_OS_4:
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# D7 D6 D5 O4 C3 C2 C1 C0 BT
|
|
dl = ctrl[0:4]
|
|
cl = [1]*4
|
|
if (data >> 36) & 0xf == O_SEQ_OS:
|
|
dl.append(XGMII_SEQ_OS)
|
|
elif (data >> 36) & 0xf == O_SIG_OS:
|
|
dl.append(XGMII_SIG_OS)
|
|
else:
|
|
dl.append(XGMII_ERROR)
|
|
cl.append(1)
|
|
for k in range(4,7):
|
|
dl.append((data >> (k+1)*8) & 0xff)
|
|
cl.append(0)
|
|
elif data & 0xff == BLOCK_TYPE_START_4:
|
|
# D7 D6 D5 C3 C2 C1 C0 BT
|
|
dl = ctrl[0:4]
|
|
cl = [1]*4
|
|
dl.append(XGMII_START)
|
|
cl.append(1)
|
|
for k in range(4,7):
|
|
dl.append((data >> (k+1)*8) & 0xff)
|
|
cl.append(0)
|
|
elif data & 0xff == BLOCK_TYPE_OS_START:
|
|
# D7 D6 D5 O0 D3 D2 D1 BT
|
|
if (data >> 32) & 0xf == O_SEQ_OS:
|
|
dl.append(XGMII_SEQ_OS)
|
|
elif (data >> 32) & 0xf == O_SIG_OS:
|
|
dl.append(XGMII_SIG_OS)
|
|
else:
|
|
dl.append(XGMII_ERROR)
|
|
cl.append(1)
|
|
for k in range(0,3):
|
|
dl.append((data >> (k+1)*8) & 0xff)
|
|
cl.append(0)
|
|
dl.append(XGMII_START)
|
|
cl.append(1)
|
|
for k in range(4,7):
|
|
dl.append((data >> (k+1)*8) & 0xff)
|
|
cl.append(0)
|
|
elif data & 0xff == BLOCK_TYPE_OS_04:
|
|
# D7 D6 D5 O4 O0 D3 D2 D1 BT
|
|
if (data >> 32) & 0xf == O_SEQ_OS:
|
|
dl.append(XGMII_SEQ_OS)
|
|
elif (data >> 32) & 0xf == O_SIG_OS:
|
|
dl.append(XGMII_SIG_OS)
|
|
else:
|
|
dl.append(XGMII_ERROR)
|
|
cl.append(1)
|
|
for k in range(0,3):
|
|
dl.append((data >> (k+1)*8) & 0xff)
|
|
cl.append(0)
|
|
if (data >> 36) & 0xf == O_SEQ_OS:
|
|
dl.append(XGMII_SEQ_OS)
|
|
elif (data >> 36) & 0xf == O_SIG_OS:
|
|
dl.append(XGMII_SIG_OS)
|
|
else:
|
|
dl.append(XGMII_ERROR)
|
|
cl.append(1)
|
|
for k in range(4,7):
|
|
dl.append((data >> (k+1)*8) & 0xff)
|
|
cl.append(0)
|
|
elif data & 0xff == BLOCK_TYPE_START_0:
|
|
# D7 D6 D5 D4 D3 D2 D1 BT
|
|
dl.append(XGMII_START)
|
|
cl.append(1)
|
|
for k in range(7):
|
|
dl.append((data >> (k+1)*8) & 0xff)
|
|
cl.append(0)
|
|
elif data & 0xff == BLOCK_TYPE_OS_0:
|
|
# C7 C6 C5 C4 O0 D3 D2 D1 BT
|
|
if (data >> 32) & 0xf == O_SEQ_OS:
|
|
dl.append(XGMII_SEQ_OS)
|
|
elif (data >> 32) & 0xf == O_SIG_OS:
|
|
dl.append(XGMII_SEQ_OS)
|
|
else:
|
|
dl.append(XGMII_ERROR)
|
|
cl.append(1)
|
|
for k in range(0,3):
|
|
dl.append((data >> (k+1)*8) & 0xff)
|
|
cl.append(0)
|
|
dl.extend(ctrl[4:8])
|
|
cl.extend([1]*4)
|
|
elif data & 0xff == BLOCK_TYPE_TERM_0:
|
|
# C7 C6 C5 C4 C3 C2 C1 BT
|
|
dl.append(XGMII_TERM)
|
|
cl.append(1)
|
|
dl.extend(ctrl[1:])
|
|
cl.extend([1]*7)
|
|
elif data & 0xff == BLOCK_TYPE_TERM_1:
|
|
# C7 C6 C5 C4 C3 C2 D0 BT
|
|
dl.append((data >> 8) & 0xff)
|
|
cl.append(0)
|
|
dl.append(XGMII_TERM)
|
|
cl.append(1)
|
|
dl.extend(ctrl[2:])
|
|
cl.extend([1]*6)
|
|
elif data & 0xff == BLOCK_TYPE_TERM_2:
|
|
# C7 C6 C5 C4 C3 D1 D0 BT
|
|
for k in range(2):
|
|
dl.append((data >> (k+1)*8) & 0xff)
|
|
cl.append(0)
|
|
dl.append(XGMII_TERM)
|
|
cl.append(1)
|
|
dl.extend(ctrl[3:])
|
|
cl.extend([1]*5)
|
|
elif data & 0xff == BLOCK_TYPE_TERM_3:
|
|
# C7 C6 C5 C4 D2 D1 D0 BT
|
|
for k in range(3):
|
|
dl.append((data >> (k+1)*8) & 0xff)
|
|
cl.append(0)
|
|
dl.append(XGMII_TERM)
|
|
cl.append(1)
|
|
dl.extend(ctrl[4:])
|
|
cl.extend([1]*4)
|
|
elif data & 0xff == BLOCK_TYPE_TERM_4:
|
|
# C7 C6 C5 D3 D2 D1 D0 BT
|
|
for k in range(4):
|
|
dl.append((data >> (k+1)*8) & 0xff)
|
|
cl.append(0)
|
|
dl.append(XGMII_TERM)
|
|
cl.append(1)
|
|
dl.extend(ctrl[5:])
|
|
cl.extend([1]*3)
|
|
elif data & 0xff == BLOCK_TYPE_TERM_5:
|
|
# C7 C6 D4 D3 D2 D1 D0 BT
|
|
for k in range(5):
|
|
dl.append((data >> (k+1)*8) & 0xff)
|
|
cl.append(0)
|
|
dl.append(XGMII_TERM)
|
|
cl.append(1)
|
|
dl.extend(ctrl[6:])
|
|
cl.extend([1]*2)
|
|
elif data & 0xff == BLOCK_TYPE_TERM_6:
|
|
# C7 D5 D4 D3 D2 D1 D0 BT
|
|
for k in range(6):
|
|
dl.append((data >> (k+1)*8) & 0xff)
|
|
cl.append(0)
|
|
dl.append(XGMII_TERM)
|
|
cl.append(1)
|
|
dl.extend(ctrl[7:])
|
|
cl.extend([1]*1)
|
|
elif data & 0xff == BLOCK_TYPE_TERM_7:
|
|
# D6 D5 D4 D3 D2 D1 D0 BT
|
|
for k in range(7):
|
|
dl.append((data >> (k+1)*8) & 0xff)
|
|
cl.append(0)
|
|
dl.append(XGMII_TERM)
|
|
cl.append(1)
|
|
else:
|
|
# invalid block type
|
|
dl = [XGMII_ERROR]*8
|
|
cl = [1]*8
|
|
else:
|
|
# invalid sync header
|
|
dl = [XGMII_ERROR]*8
|
|
cl = [1]*8
|
|
|
|
if frame is None:
|
|
if cl[0] and dl[0] == XGMII_START:
|
|
# start in lane 0
|
|
frame = xgmii_ep.XGMIIFrame()
|
|
d = [ETH_PRE]
|
|
c = [0]
|
|
for i in range(1,bw):
|
|
d.append(dl[i])
|
|
c.append(cl[i])
|
|
elif bw == 8 and cl[4] and dl[4] == XGMII_START:
|
|
# start in lane 4
|
|
frame = xgmii_ep.XGMIIFrame()
|
|
d = [ETH_PRE]
|
|
c = [0]
|
|
for i in range(5,bw):
|
|
d.append(dl[i])
|
|
c.append(cl[i])
|
|
else:
|
|
for i in range(bw):
|
|
if cl[i]:
|
|
# got a control character; terminate frame reception
|
|
if dl[i] != XGMII_TERM:
|
|
# store control character if it's not a termination
|
|
d.append(dl[i])
|
|
c.append(cl[i])
|
|
frame.parse(d, c)
|
|
self.queue.append(frame)
|
|
self.sync.next = not self.sync
|
|
if name is not None:
|
|
print("[%s] Got frame %s" % (name, repr(frame)))
|
|
frame = None
|
|
d = []
|
|
c = []
|
|
break
|
|
else:
|
|
d.append(dl[i])
|
|
c.append(cl[i])
|
|
|
|
return instances()
|
|
|