FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-14 06:43:18 +08:00
Code Issues Projects Releases Wiki Activity
22 Commits 1 Branch 0 Tags
Go to file
Clone
Open with VS Code Open with VSCodium Open with Intellij IDEA
Download ZIP Download TAR.GZ Download BUNDLE
Alex Forencich e8c43653e3 Adjust syntax for old Python 2
2014-11-05 16:33:33 -08:00
rtl
Separate out input mux in AXI frame joiner
2014-10-28 01:55:42 -07:00
tb
Adjust syntax for old Python 2
2014-11-05 16:33:33 -08:00
.gitignore
Initial commit
2014-09-13 21:17:57 -07:00
.travis.yml
Add .travis.yml
2014-11-05 16:22:09 -08:00
AUTHORS
Initial commit
2014-09-13 21:17:57 -07:00
COPYING
Initial commit
2014-09-13 21:17:57 -07:00
README
Update readme
2014-11-05 16:19:00 -08:00

README 

Verilog AXI Stream components
Description
No description provided
Readme 106 MiB
Languages
Verilog 46.2%
Python 32.5%
Tcl 13.9%
Makefile 7.3%