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verilog-ethernet/rtl
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Alex Forencich 24f7aee8b2 Add COBS encoder and decoder modules and testbench
2016-08-21 20:03:54 -07:00
..
arbiter.v
Happy new year
2016-01-05 00:24:20 -08:00
axis_adapter.v
Adjust constant naming
2016-06-27 11:27:04 -07:00
axis_arb_mux_4.v
Happy new year
2016-01-05 00:24:20 -08:00
axis_arb_mux_64_4.v
Happy new year
2016-01-05 00:24:20 -08:00
axis_arb_mux_64.py
Happy new year
2016-01-05 00:24:20 -08:00
axis_arb_mux.py
Happy new year
2016-01-05 00:24:20 -08:00
axis_async_fifo_64.v
Add FIFO output pipeline registers to aid block RAM output timing closure
2016-08-04 18:03:00 -07:00
axis_async_fifo.v
Add FIFO output pipeline registers to aid block RAM output timing closure
2016-08-04 18:03:00 -07:00
axis_async_frame_fifo_64.v
Add FIFO output pipeline registers to aid block RAM output timing closure
2016-08-04 18:03:00 -07:00
axis_async_frame_fifo.v
Add FIFO output pipeline registers to aid block RAM output timing closure
2016-08-04 18:03:00 -07:00
axis_cobs_decode.v
Add COBS encoder and decoder modules and testbench
2016-08-21 20:03:54 -07:00
axis_cobs_encode.v
Add COBS encoder and decoder modules and testbench
2016-08-21 20:03:54 -07:00
axis_crosspoint_4x4.v
Happy new year
2016-01-05 00:24:20 -08:00
axis_crosspoint_64_4x4.v
Happy new year
2016-01-05 00:24:20 -08:00
axis_crosspoint_64.py
Support generating asymmetric crosspoints
2016-07-24 13:06:59 -07:00
axis_crosspoint.py
Support generating asymmetric crosspoints
2016-07-24 13:06:59 -07:00
axis_demux_4.v
Happy new year
2016-01-05 00:24:20 -08:00
axis_demux_64_4.v
Happy new year
2016-01-05 00:24:20 -08:00
axis_demux_64.py
Happy new year
2016-01-05 00:24:20 -08:00
axis_demux.py
Happy new year
2016-01-05 00:24:20 -08:00
axis_fifo_64.v
Add FIFO output pipeline registers to aid block RAM output timing closure
2016-08-04 18:03:00 -07:00
axis_fifo.v
Add FIFO output pipeline registers to aid block RAM output timing closure
2016-08-04 18:03:00 -07:00
axis_frame_fifo_64.v
Add FIFO output pipeline registers to aid block RAM output timing closure
2016-08-04 18:03:00 -07:00
axis_frame_fifo.v
Add FIFO output pipeline registers to aid block RAM output timing closure
2016-08-04 18:03:00 -07:00
axis_frame_join_4.v
Happy new year
2016-01-05 00:24:20 -08:00
axis_frame_join.py
Happy new year
2016-01-05 00:24:20 -08:00
axis_frame_length_adjust_fifo_64.v
Fix default width
2016-06-27 11:24:36 -07:00
axis_frame_length_adjust_fifo.v
Happy new year
2016-01-05 00:24:20 -08:00
axis_frame_length_adjust.v
Assume first tkeep bit is always set
2016-07-20 12:36:59 -07:00
axis_ll_bridge.v
Happy new year
2016-01-05 00:24:20 -08:00
axis_mux_4.v
Happy new year
2016-01-05 00:24:20 -08:00
axis_mux_64_4.v
Happy new year
2016-01-05 00:24:20 -08:00
axis_mux_64.py
Happy new year
2016-01-05 00:24:20 -08:00
axis_mux.py
Happy new year
2016-01-05 00:24:20 -08:00
axis_rate_limit_64.v
Happy new year
2016-01-05 00:24:20 -08:00
axis_rate_limit.v
Happy new year
2016-01-05 00:24:20 -08:00
axis_register_64.v
Happy new year
2016-01-05 00:24:20 -08:00
axis_register.v
Happy new year
2016-01-05 00:24:20 -08:00
axis_srl_fifo_64.v
Remove reset dependence
2016-06-27 11:26:15 -07:00
axis_srl_fifo.v
Remove reset dependence
2016-06-27 11:26:15 -07:00
axis_srl_register_64.v
Happy new year
2016-01-05 00:24:20 -08:00
axis_srl_register.v
Happy new year
2016-01-05 00:24:20 -08:00
axis_stat_counter.v
Happy new year
2016-01-05 00:24:20 -08:00
axis_switch_4x4.v
Add AXI stream switch module, generator script, and testbench
2016-07-25 13:12:10 -07:00
axis_switch_64_4x4.v
Add AXI stream switch module, generator script, and testbench
2016-07-25 13:12:10 -07:00
axis_switch_64.py
Add AXI stream switch module, generator script, and testbench
2016-07-25 13:12:10 -07:00
axis_switch.py
Add AXI stream switch module, generator script, and testbench
2016-07-25 13:12:10 -07:00
axis_tap_64.v
Happy new year
2016-01-05 00:24:20 -08:00
axis_tap.v
Happy new year
2016-01-05 00:24:20 -08:00
ll_axis_bridge.v
Happy new year
2016-01-05 00:24:20 -08:00
priority_encoder.v
Happy new year
2016-01-05 00:24:20 -08:00