mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-14 06:43:18 +08:00
334 lines
9.2 KiB
Verilog
334 lines
9.2 KiB
Verilog
/*
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Copyright (c) 2015-2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* 1G Ethernet MAC with RGMII interface and TX and RX FIFOs
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*/
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module eth_mac_1g_rgmii_fifo #
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(
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// target ("SIM", "GENERIC", "XILINX", "ALTERA")
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parameter TARGET = "GENERIC",
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// IODDR style ("IODDR", "IODDR2")
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// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
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// Use IODDR2 for Spartan-6
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parameter IODDR_STYLE = "IODDR2",
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// Clock input style ("BUFG", "BUFR", "BUFIO", "BUFIO2")
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// Use BUFR for Virtex-5, Virtex-6, 7-series
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// Use BUFG for Ultrascale
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// Use BUFIO2 for Spartan-6
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parameter CLOCK_INPUT_STYLE = "BUFIO2",
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// Use 90 degree clock for RGMII transmit ("TRUE", "FALSE")
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parameter USE_CLK90 = "TRUE",
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parameter ENABLE_PADDING = 1,
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parameter MIN_FRAME_LENGTH = 64,
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parameter TX_FIFO_ADDR_WIDTH = 12,
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parameter TX_FRAME_FIFO = 1,
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parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO,
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parameter TX_DROP_WHEN_FULL = 0,
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parameter RX_FIFO_ADDR_WIDTH = 12,
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parameter RX_FRAME_FIFO = 1,
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parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO,
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parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO
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)
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(
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input wire gtx_clk,
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input wire gtx_clk90,
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input wire gtx_rst,
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input wire logic_clk,
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input wire logic_rst,
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/*
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* AXI input
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*/
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input wire [7:0] tx_axis_tdata,
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input wire tx_axis_tvalid,
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output wire tx_axis_tready,
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input wire tx_axis_tlast,
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input wire tx_axis_tuser,
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/*
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* AXI output
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*/
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output wire [7:0] rx_axis_tdata,
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output wire rx_axis_tvalid,
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input wire rx_axis_tready,
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output wire rx_axis_tlast,
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output wire rx_axis_tuser,
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/*
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* RGMII interface
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*/
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input wire rgmii_rx_clk,
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input wire [3:0] rgmii_rxd,
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input wire rgmii_rx_ctl,
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output wire rgmii_tx_clk,
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output wire [3:0] rgmii_txd,
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output wire rgmii_tx_ctl,
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/*
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* Status
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*/
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output wire tx_error_underflow,
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output wire tx_fifo_overflow,
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output wire tx_fifo_bad_frame,
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output wire tx_fifo_good_frame,
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output wire rx_error_bad_frame,
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output wire rx_error_bad_fcs,
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output wire rx_fifo_overflow,
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output wire rx_fifo_bad_frame,
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output wire rx_fifo_good_frame,
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output wire [1:0] speed,
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/*
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* Configuration
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*/
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input wire [7:0] ifg_delay
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);
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wire tx_clk;
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wire rx_clk;
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wire tx_rst;
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wire rx_rst;
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wire [7:0] tx_fifo_axis_tdata;
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wire tx_fifo_axis_tvalid;
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wire tx_fifo_axis_tready;
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wire tx_fifo_axis_tlast;
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wire tx_fifo_axis_tuser;
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wire [7:0] rx_fifo_axis_tdata;
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wire rx_fifo_axis_tvalid;
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wire rx_fifo_axis_tlast;
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wire rx_fifo_axis_tuser;
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// synchronize MAC status signals into logic clock domain
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wire tx_error_underflow_int;
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reg tx_sync_reg_1 = 1'b0;
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reg tx_sync_reg_2 = 1'b0;
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reg tx_sync_reg_3 = 1'b0;
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reg tx_sync_reg_4 = 1'b0;
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assign tx_error_underflow = tx_sync_reg_3 ^ tx_sync_reg_4;
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always @(posedge tx_clk or posedge tx_rst) begin
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if (tx_rst) begin
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tx_sync_reg_1 <= 1'b0;
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end else begin
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tx_sync_reg_1 <= tx_sync_reg_1 ^ {tx_error_underflow_int};
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end
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end
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always @(posedge logic_clk or posedge logic_rst) begin
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if (logic_rst) begin
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tx_sync_reg_2 <= 1'b0;
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tx_sync_reg_3 <= 1'b0;
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tx_sync_reg_4 <= 1'b0;
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end else begin
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tx_sync_reg_2 <= tx_sync_reg_1;
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tx_sync_reg_3 <= tx_sync_reg_2;
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tx_sync_reg_4 <= tx_sync_reg_3;
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end
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end
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wire rx_error_bad_frame_int;
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wire rx_error_bad_fcs_int;
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reg [1:0] rx_sync_reg_1 = 2'd0;
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reg [1:0] rx_sync_reg_2 = 2'd0;
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reg [1:0] rx_sync_reg_3 = 2'd0;
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reg [1:0] rx_sync_reg_4 = 2'd0;
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assign rx_error_bad_frame = rx_sync_reg_3[0] ^ rx_sync_reg_4[0];
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assign rx_error_bad_fcs = rx_sync_reg_3[1] ^ rx_sync_reg_4[1];
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always @(posedge rx_clk or posedge rx_rst) begin
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if (rx_rst) begin
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rx_sync_reg_1 <= 2'd0;
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end else begin
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rx_sync_reg_1 <= rx_sync_reg_1 ^ {rx_error_bad_frame_int, rx_error_bad_frame_int};
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end
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end
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always @(posedge logic_clk or posedge logic_rst) begin
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if (logic_rst) begin
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rx_sync_reg_2 <= 2'd0;
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rx_sync_reg_3 <= 2'd0;
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rx_sync_reg_4 <= 2'd0;
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end else begin
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rx_sync_reg_2 <= rx_sync_reg_1;
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rx_sync_reg_3 <= rx_sync_reg_2;
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rx_sync_reg_4 <= rx_sync_reg_3;
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end
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end
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wire [1:0] speed_int;
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reg [1:0] speed_sync_reg_1 = 2'b10;
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reg [1:0] speed_sync_reg_2 = 2'b10;
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assign speed = speed_sync_reg_2;
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always @(posedge logic_clk) begin
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speed_sync_reg_1 <= speed_int;
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speed_sync_reg_2 <= speed_sync_reg_1;
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end
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eth_mac_1g_rgmii #(
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.TARGET(TARGET),
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.IODDR_STYLE(IODDR_STYLE),
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.CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE),
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.USE_CLK90(USE_CLK90),
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.ENABLE_PADDING(ENABLE_PADDING),
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.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
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)
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eth_mac_1g_rgmii_inst (
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.gtx_clk(gtx_clk),
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.gtx_clk90(gtx_clk90),
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.gtx_rst(gtx_rst),
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.tx_clk(tx_clk),
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.tx_rst(tx_rst),
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.rx_clk(rx_clk),
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.rx_rst(rx_rst),
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.tx_axis_tdata(tx_fifo_axis_tdata),
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.tx_axis_tvalid(tx_fifo_axis_tvalid),
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.tx_axis_tready(tx_fifo_axis_tready),
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.tx_axis_tlast(tx_fifo_axis_tlast),
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.tx_axis_tuser(tx_fifo_axis_tuser),
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.rx_axis_tdata(rx_fifo_axis_tdata),
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.rx_axis_tvalid(rx_fifo_axis_tvalid),
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.rx_axis_tlast(rx_fifo_axis_tlast),
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.rx_axis_tuser(rx_fifo_axis_tuser),
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.rgmii_rx_clk(rgmii_rx_clk),
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.rgmii_rxd(rgmii_rxd),
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.rgmii_rx_ctl(rgmii_rx_ctl),
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.rgmii_tx_clk(rgmii_tx_clk),
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.rgmii_txd(rgmii_txd),
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.rgmii_tx_ctl(rgmii_tx_ctl),
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.rx_error_bad_frame(rx_error_bad_frame_int),
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.rx_error_bad_fcs(rx_error_bad_fcs_int),
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.speed(speed_int),
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.ifg_delay(ifg_delay)
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);
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axis_async_fifo #(
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.ADDR_WIDTH(TX_FIFO_ADDR_WIDTH),
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.DATA_WIDTH(8),
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.KEEP_ENABLE(0),
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.LAST_ENABLE(1),
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.ID_ENABLE(0),
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.DEST_ENABLE(0),
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.USER_ENABLE(1),
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.USER_WIDTH(1),
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.FRAME_FIFO(TX_FRAME_FIFO),
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.USER_BAD_FRAME_VALUE(1'b1),
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.USER_BAD_FRAME_MASK(1'b1),
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.DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
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.DROP_WHEN_FULL(TX_DROP_WHEN_FULL)
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)
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tx_fifo (
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// Common reset
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.async_rst(logic_rst | tx_rst),
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// AXI input
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.s_clk(logic_clk),
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.s_axis_tdata(tx_axis_tdata),
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.s_axis_tkeep(0),
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.s_axis_tvalid(tx_axis_tvalid),
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.s_axis_tready(tx_axis_tready),
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.s_axis_tlast(tx_axis_tlast),
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.s_axis_tid(0),
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.s_axis_tdest(0),
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.s_axis_tuser(tx_axis_tuser),
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// AXI output
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.m_clk(tx_clk),
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.m_axis_tdata(tx_fifo_axis_tdata),
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.m_axis_tkeep(),
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.m_axis_tvalid(tx_fifo_axis_tvalid),
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.m_axis_tready(tx_fifo_axis_tready),
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.m_axis_tlast(tx_fifo_axis_tlast),
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.m_axis_tid(),
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.m_axis_tdest(),
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.m_axis_tuser(tx_fifo_axis_tuser),
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// Status
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.s_status_overflow(tx_fifo_overflow),
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.s_status_bad_frame(tx_fifo_bad_frame),
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.s_status_good_frame(tx_fifo_good_frame),
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.m_status_overflow(),
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.m_status_bad_frame(),
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.m_status_good_frame()
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);
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axis_async_fifo #(
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.ADDR_WIDTH(RX_FIFO_ADDR_WIDTH),
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.DATA_WIDTH(8),
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.KEEP_ENABLE(0),
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.LAST_ENABLE(1),
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.ID_ENABLE(0),
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.DEST_ENABLE(0),
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.USER_ENABLE(1),
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.USER_WIDTH(1),
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.FRAME_FIFO(TX_FRAME_FIFO),
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.USER_BAD_FRAME_VALUE(1'b1),
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.USER_BAD_FRAME_MASK(1'b1),
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.DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
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.DROP_WHEN_FULL(TX_DROP_WHEN_FULL)
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)
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rx_fifo (
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// Common reset
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.async_rst(rx_rst | logic_rst),
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// AXI input
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.s_clk(rx_clk),
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.s_axis_tdata(rx_fifo_axis_tdata),
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.s_axis_tkeep(0),
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.s_axis_tvalid(rx_fifo_axis_tvalid),
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.s_axis_tready(),
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.s_axis_tlast(rx_fifo_axis_tlast),
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.s_axis_tid(0),
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.s_axis_tdest(0),
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.s_axis_tuser(rx_fifo_axis_tuser),
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// AXI output
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.m_clk(logic_clk),
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.m_axis_tdata(rx_axis_tdata),
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.m_axis_tkeep(),
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.m_axis_tvalid(rx_axis_tvalid),
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.m_axis_tready(rx_axis_tready),
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.m_axis_tlast(rx_axis_tlast),
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.m_axis_tid(),
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.m_axis_tdest(),
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.m_axis_tuser(rx_axis_tuser),
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// Status
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.s_status_overflow(),
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.s_status_bad_frame(),
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.s_status_good_frame(),
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.m_status_overflow(rx_fifo_overflow),
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.m_status_bad_frame(rx_fifo_bad_frame),
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.m_status_good_frame(rx_fifo_good_frame)
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);
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endmodule
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