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verilog-ethernet/example/HTG9200
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Alex Forencich efb3747967 Add IO delay false paths to HTG-9200 constraints file 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-07-20 21:15:20 -07:00
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fpga_25g
Add IO delay false paths to HTG-9200 constraints file
2023-07-20 21:15:20 -07:00