FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-28 07:03:08 +08:00
Code Issues Projects Releases Wiki Activity
verilog-ethernet/example/fb2CG/fpga_25g/common
History
Alex Forencich 412df8fea0 Use unified 10G/25G design for fb2CG@KU15P 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-07-13 21:34:53 -07:00
..
vivado.mk
Use unified 10G/25G design for fb2CG@KU15P
2023-07-13 21:34:53 -07:00