mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-02-04 07:13:13 +08:00
326 lines
8.2 KiB
Verilog
326 lines
8.2 KiB
Verilog
/*
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Copyright (c) 2014-2021 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* FPGA top-level module
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*/
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module fpga #
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(
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parameter QUAD_CNT = 17,
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parameter CH_CNT = QUAD_CNT*4
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)
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(
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/*
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* Clock: 156.25MHz
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*/
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input wire [1:0] refclk_user_p,
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input wire [1:0] refclk_user_n,
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/*
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* Ethernet: QSFP28
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*/
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input wire [CH_CNT-1:0] eth_gt_ch_rx_p,
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input wire [CH_CNT-1:0] eth_gt_ch_rx_n,
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output wire [CH_CNT-1:0] eth_gt_ch_tx_p,
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output wire [CH_CNT-1:0] eth_gt_ch_tx_n,
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input wire [QUAD_CNT-1:0] eth_gt_pri_refclk_p,
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input wire [QUAD_CNT-1:0] eth_gt_pri_refclk_n
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);
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genvar n;
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// Clock and reset
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// Buffers
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wire [1:0] refclk_user;
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generate
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for (n = 0; n < 2; n = n + 1) begin : refclk_buf
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IBUFGDS #(
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.DIFF_TERM("FALSE"),
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.IBUF_LOW_PWR("FALSE")
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)
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refclk_ibufg_inst (
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.O (refclk_user[n]),
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.I (refclk_user_p[n]),
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.IB (refclk_user_n[n])
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);
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end
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endgenerate
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// Internal 125 MHz clock
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wire clk_125mhz_mmcm_out;
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wire clk_125mhz_int;
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wire rst_125mhz_int;
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// Internal 156.25 MHz clock
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wire clk_156mhz_int;
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wire rst_156mhz_int;
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wire mmcm_rst = 1'b0;
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wire mmcm_locked;
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wire mmcm_clkfb;
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// MMCM instance
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// 156.25 MHz in, 125 MHz out
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// PFD range: 10 MHz to 500 MHz
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// VCO range: 800 MHz to 1600 MHz
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// M = 8, D = 1 sets Fvco = 1250 MHz
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// Divide by 10 to get output frequency of 125 MHz
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MMCME3_BASE #(
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.BANDWIDTH("OPTIMIZED"),
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.CLKOUT0_DIVIDE_F(10),
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT0_PHASE(0),
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.CLKOUT1_DIVIDE(1),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT1_PHASE(0),
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.CLKOUT2_DIVIDE(1),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT2_PHASE(0),
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.CLKOUT3_DIVIDE(1),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT3_PHASE(0),
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.CLKOUT4_DIVIDE(1),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT4_PHASE(0),
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.CLKOUT5_DIVIDE(1),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT5_PHASE(0),
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.CLKOUT6_DIVIDE(1),
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.CLKOUT6_DUTY_CYCLE(0.5),
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.CLKOUT6_PHASE(0),
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.CLKFBOUT_MULT_F(8),
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.CLKFBOUT_PHASE(0),
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.DIVCLK_DIVIDE(1),
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.REF_JITTER1(0.010),
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.CLKIN1_PERIOD(6.400),
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.STARTUP_WAIT("FALSE"),
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.CLKOUT4_CASCADE("FALSE")
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)
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clk_mmcm_inst (
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.CLKIN1(refclk_user[0]),
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.CLKFBIN(mmcm_clkfb),
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.RST(mmcm_rst),
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.PWRDWN(1'b0),
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.CLKOUT0(clk_125mhz_mmcm_out),
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.CLKOUT0B(),
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.CLKOUT1(),
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.CLKOUT1B(),
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.CLKOUT2(),
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.CLKOUT2B(),
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.CLKOUT3(),
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.CLKOUT3B(),
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.CLKOUT4(),
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.CLKOUT5(),
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.CLKOUT6(),
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.CLKFBOUT(mmcm_clkfb),
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.CLKFBOUTB(),
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.LOCKED(mmcm_locked)
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);
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BUFG
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clk_125mhz_bufg_inst (
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.I(clk_125mhz_mmcm_out),
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.O(clk_125mhz_int)
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);
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sync_reset #(
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.N(4)
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)
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sync_reset_125mhz_inst (
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.clk(clk_125mhz_int),
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.rst(~mmcm_locked),
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.out(rst_125mhz_int)
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);
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// XGMII 10G PHY
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wire [CH_CNT-1:0] eth_tx_clk;
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wire [CH_CNT-1:0] eth_tx_rst;
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wire [CH_CNT*64-1:0] eth_txd;
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wire [CH_CNT*8-1:0] eth_txc;
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wire [CH_CNT-1:0] eth_rx_clk;
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wire [CH_CNT-1:0] eth_rx_rst;
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wire [CH_CNT*64-1:0] eth_rxd;
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wire [CH_CNT*8-1:0] eth_rxc;
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assign clk_156mhz_int = eth_tx_clk[0];
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assign rst_156mhz_int = eth_tx_rst[0];
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generate
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for (n = 0; n < QUAD_CNT; n = n + 1) begin : eth_quad
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wire quad_mgt_refclk;
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IBUFDS_GTE4 ibufds_gte4_qsfp_1_mgt_refclk_inst (
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.I (eth_gt_pri_refclk_p[n]),
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.IB (eth_gt_pri_refclk_n[n]),
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.CEB (1'b0),
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.O (quad_mgt_refclk),
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.ODIV2 ()
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);
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eth_xcvr_phy_quad_wrapper
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quad_phy_inst (
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.xcvr_ctrl_clk(clk_125mhz_int),
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.xcvr_ctrl_rst(rst_125mhz_int),
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/*
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* Common
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*/
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.xcvr_gtpowergood_out(),
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/*
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* PLL
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*/
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.xcvr_gtrefclk00_in(quad_mgt_refclk),
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/*
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* Serial data
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*/
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.xcvr_txp(eth_gt_ch_tx_p[n*4 +: 4]),
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.xcvr_txn(eth_gt_ch_tx_n[n*4 +: 4]),
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.xcvr_rxp(eth_gt_ch_rx_p[n*4 +: 4]),
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.xcvr_rxn(eth_gt_ch_rx_n[n*4 +: 4]),
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/*
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* PHY connections
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*/
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.phy_1_tx_clk(eth_tx_clk[n*4+0 +: 1]),
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.phy_1_tx_rst(eth_tx_rst[n*4+0 +: 1]),
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.phy_1_xgmii_txd(eth_txd[(n*4+0)*64 +: 64]),
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.phy_1_xgmii_txc(eth_txc[(n*4+0)*8 +: 8]),
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.phy_1_rx_clk(eth_rx_clk[n*4+0 +: 1]),
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.phy_1_rx_rst(eth_rx_rst[n*4+0 +: 1]),
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.phy_1_xgmii_rxd(eth_rxd[(n*4+0)*64 +: 64]),
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.phy_1_xgmii_rxc(eth_rxc[(n*4+0)*8 +: 8]),
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.phy_1_tx_bad_block(),
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.phy_1_rx_error_count(),
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.phy_1_rx_bad_block(),
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.phy_1_rx_sequence_error(),
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.phy_1_rx_block_lock(),
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.phy_1_rx_high_ber(),
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.phy_1_rx_status(),
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.phy_1_cfg_tx_prbs31_enable(1'b0),
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.phy_1_cfg_rx_prbs31_enable(1'b0),
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.phy_2_tx_clk(eth_tx_clk[n*4+1 +: 1]),
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.phy_2_tx_rst(eth_tx_rst[n*4+1 +: 1]),
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.phy_2_xgmii_txd(eth_txd[(n*4+1)*64 +: 64]),
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.phy_2_xgmii_txc(eth_txc[(n*4+1)*8 +: 8]),
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.phy_2_rx_clk(eth_rx_clk[n*4+1 +: 1]),
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.phy_2_rx_rst(eth_rx_rst[n*4+1 +: 1]),
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.phy_2_xgmii_rxd(eth_rxd[(n*4+1)*64 +: 64]),
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.phy_2_xgmii_rxc(eth_rxc[(n*4+1)*8 +: 8]),
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.phy_2_tx_bad_block(),
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.phy_2_rx_error_count(),
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.phy_2_rx_bad_block(),
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.phy_2_rx_sequence_error(),
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.phy_2_rx_block_lock(),
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.phy_2_rx_high_ber(),
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.phy_2_rx_status(),
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.phy_2_cfg_tx_prbs31_enable(1'b0),
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.phy_2_cfg_rx_prbs31_enable(1'b0),
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.phy_3_tx_clk(eth_tx_clk[n*4+2 +: 1]),
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.phy_3_tx_rst(eth_tx_rst[n*4+2 +: 1]),
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.phy_3_xgmii_txd(eth_txd[(n*4+2)*64 +: 64]),
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.phy_3_xgmii_txc(eth_txc[(n*4+2)*8 +: 8]),
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.phy_3_rx_clk(eth_rx_clk[n*4+2 +: 1]),
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.phy_3_rx_rst(eth_rx_rst[n*4+2 +: 1]),
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.phy_3_xgmii_rxd(eth_rxd[(n*4+2)*64 +: 64]),
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.phy_3_xgmii_rxc(eth_rxc[(n*4+2)*8 +: 8]),
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.phy_3_tx_bad_block(),
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.phy_3_rx_error_count(),
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.phy_3_rx_bad_block(),
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.phy_3_rx_sequence_error(),
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.phy_3_rx_block_lock(),
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.phy_3_rx_high_ber(),
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.phy_3_rx_status(),
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.phy_3_cfg_tx_prbs31_enable(1'b0),
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.phy_3_cfg_rx_prbs31_enable(1'b0),
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.phy_4_tx_clk(eth_tx_clk[n*4+3 +: 1]),
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.phy_4_tx_rst(eth_tx_rst[n*4+3 +: 1]),
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.phy_4_xgmii_txd(eth_txd[(n*4+3)*64 +: 64]),
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.phy_4_xgmii_txc(eth_txc[(n*4+3)*8 +: 8]),
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.phy_4_rx_clk(eth_rx_clk[n*4+3 +: 1]),
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.phy_4_rx_rst(eth_rx_rst[n*4+3 +: 1]),
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.phy_4_xgmii_rxd(eth_rxd[(n*4+3)*64 +: 64]),
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.phy_4_xgmii_rxc(eth_rxc[(n*4+3)*8 +: 8]),
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.phy_4_tx_bad_block(),
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.phy_4_rx_error_count(),
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.phy_4_rx_bad_block(),
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.phy_4_rx_sequence_error(),
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.phy_4_rx_block_lock(),
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.phy_4_rx_high_ber(),
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.phy_4_rx_status(),
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.phy_4_cfg_tx_prbs31_enable(1'b0),
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.phy_4_cfg_rx_prbs31_enable(1'b0)
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);
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end
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endgenerate
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fpga_core #(
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.CH_CNT(CH_CNT)
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)
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core_inst (
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/*
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* Clock: 156.25 MHz
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* Synchronous reset
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*/
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.clk(clk_156mhz_int),
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.rst(rst_156mhz_int),
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/*
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* Ethernet: QSFP28
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*/
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.eth_tx_clk(eth_tx_clk),
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.eth_tx_rst(eth_tx_rst),
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.eth_txd(eth_txd),
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.eth_txc(eth_txc),
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.eth_rx_clk(eth_rx_clk),
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.eth_rx_rst(eth_rx_rst),
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.eth_rxd(eth_rxd),
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.eth_rxc(eth_rxc)
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);
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endmodule
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`resetall
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