verilog-ethernet/clock.xdc at f0c47db509d8e2ee75c04735207674527bbb9390 - verilog-ethernet - Gitea: Git with a cup of tea

FPGA/verilog-ethernet

mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-28 07:03:08 +08:00

Alex Forencich 1d61626785 Add KC705 GMII example design

2019-05-02 19:29:47 -07:00

5 lines

116 B

Tcl

Raw Blame History

 # Clock constraints
 # BUFGMUX outputs
 set_clock_groups -physically_exclusive -group clk_mmcm_out -group phy_tx_clk