mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-02-04 07:13:13 +08:00
396 lines
13 KiB
Verilog
396 lines
13 KiB
Verilog
/*
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Copyright (c) 2023 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Transceiver and PHY quad wrapper
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*/
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module eth_xcvr_phy_quad_wrapper #
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(
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parameter COUNT = 4,
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parameter DATA_WIDTH = 64,
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parameter CTRL_WIDTH = (DATA_WIDTH/8),
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parameter HDR_WIDTH = 2,
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parameter PRBS31_ENABLE = 0,
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parameter TX_SERDES_PIPELINE = 0,
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parameter RX_SERDES_PIPELINE = 0,
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parameter BITSLIP_HIGH_CYCLES = 1,
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parameter BITSLIP_LOW_CYCLES = 8,
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parameter COUNT_125US = 125000/6.4
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)
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(
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input wire xcvr_ctrl_clk,
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input wire xcvr_ctrl_rst,
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/*
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* Common
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*/
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output wire xcvr_gtpowergood_out,
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/*
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* PLL
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*/
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input wire xcvr_gtrefclk00_in,
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/*
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* Serial data
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*/
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output wire [COUNT-1:0] xcvr_txp,
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output wire [COUNT-1:0] xcvr_txn,
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input wire [COUNT-1:0] xcvr_rxp,
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input wire [COUNT-1:0] xcvr_rxn,
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/*
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* PHY connections
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*/
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output wire phy_1_tx_clk,
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output wire phy_1_tx_rst,
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input wire [DATA_WIDTH-1:0] phy_1_xgmii_txd,
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input wire [CTRL_WIDTH-1:0] phy_1_xgmii_txc,
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output wire phy_1_rx_clk,
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output wire phy_1_rx_rst,
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output wire [DATA_WIDTH-1:0] phy_1_xgmii_rxd,
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output wire [CTRL_WIDTH-1:0] phy_1_xgmii_rxc,
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output wire phy_1_tx_bad_block,
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output wire [6:0] phy_1_rx_error_count,
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output wire phy_1_rx_bad_block,
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output wire phy_1_rx_sequence_error,
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output wire phy_1_rx_block_lock,
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output wire phy_1_rx_high_ber,
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output wire phy_1_rx_status,
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input wire phy_1_cfg_tx_prbs31_enable,
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input wire phy_1_cfg_rx_prbs31_enable,
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output wire phy_2_tx_clk,
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output wire phy_2_tx_rst,
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input wire [DATA_WIDTH-1:0] phy_2_xgmii_txd,
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input wire [CTRL_WIDTH-1:0] phy_2_xgmii_txc,
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output wire phy_2_rx_clk,
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output wire phy_2_rx_rst,
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output wire [DATA_WIDTH-1:0] phy_2_xgmii_rxd,
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output wire [CTRL_WIDTH-1:0] phy_2_xgmii_rxc,
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output wire phy_2_tx_bad_block,
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output wire [6:0] phy_2_rx_error_count,
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output wire phy_2_rx_bad_block,
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output wire phy_2_rx_sequence_error,
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output wire phy_2_rx_block_lock,
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output wire phy_2_rx_high_ber,
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output wire phy_2_rx_status,
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input wire phy_2_cfg_tx_prbs31_enable,
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input wire phy_2_cfg_rx_prbs31_enable,
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output wire phy_3_tx_clk,
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output wire phy_3_tx_rst,
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input wire [DATA_WIDTH-1:0] phy_3_xgmii_txd,
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input wire [CTRL_WIDTH-1:0] phy_3_xgmii_txc,
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output wire phy_3_rx_clk,
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output wire phy_3_rx_rst,
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output wire [DATA_WIDTH-1:0] phy_3_xgmii_rxd,
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output wire [CTRL_WIDTH-1:0] phy_3_xgmii_rxc,
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output wire phy_3_tx_bad_block,
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output wire [6:0] phy_3_rx_error_count,
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output wire phy_3_rx_bad_block,
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output wire phy_3_rx_sequence_error,
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output wire phy_3_rx_block_lock,
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output wire phy_3_rx_high_ber,
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output wire phy_3_rx_status,
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input wire phy_3_cfg_tx_prbs31_enable,
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input wire phy_3_cfg_rx_prbs31_enable,
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output wire phy_4_tx_clk,
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output wire phy_4_tx_rst,
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input wire [DATA_WIDTH-1:0] phy_4_xgmii_txd,
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input wire [CTRL_WIDTH-1:0] phy_4_xgmii_txc,
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output wire phy_4_rx_clk,
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output wire phy_4_rx_rst,
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output wire [DATA_WIDTH-1:0] phy_4_xgmii_rxd,
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output wire [CTRL_WIDTH-1:0] phy_4_xgmii_rxc,
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output wire phy_4_tx_bad_block,
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output wire [6:0] phy_4_rx_error_count,
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output wire phy_4_rx_bad_block,
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output wire phy_4_rx_sequence_error,
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output wire phy_4_rx_block_lock,
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output wire phy_4_rx_high_ber,
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output wire phy_4_rx_status,
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input wire phy_4_cfg_tx_prbs31_enable,
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input wire phy_4_cfg_rx_prbs31_enable
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);
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generate
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wire xcvr_qpll0lock;
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wire xcvr_qpll0clk;
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wire xcvr_qpll0refclk;
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if (COUNT > 0) begin : phy1
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eth_xcvr_phy_wrapper #(
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.HAS_COMMON(1),
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.DATA_WIDTH(DATA_WIDTH),
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.CTRL_WIDTH(CTRL_WIDTH),
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.HDR_WIDTH(HDR_WIDTH),
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.PRBS31_ENABLE(PRBS31_ENABLE),
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.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
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.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
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.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
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.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
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.COUNT_125US(COUNT_125US)
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)
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eth_xcvr_phy_1 (
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.xcvr_ctrl_clk(xcvr_ctrl_clk),
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.xcvr_ctrl_rst(xcvr_ctrl_rst),
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// Common
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.xcvr_gtpowergood_out(xcvr_gtpowergood_out),
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// PLL out
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.xcvr_gtrefclk00_in(xcvr_gtrefclk00_in),
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.xcvr_qpll0lock_out(xcvr_qpll0lock),
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.xcvr_qpll0clk_out(xcvr_qpll0clk),
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.xcvr_qpll0refclk_out(xcvr_qpll0refclk),
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// PLL in
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.xcvr_qpll0lock_in(1'b0),
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.xcvr_qpll0clk_in(1'b0),
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.xcvr_qpll0refclk_in(1'b0),
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// Serial data
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.xcvr_txp(xcvr_txp[0]),
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.xcvr_txn(xcvr_txn[0]),
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.xcvr_rxp(xcvr_rxp[0]),
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.xcvr_rxn(xcvr_rxn[0]),
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// PHY connections
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.phy_tx_clk(phy_1_tx_clk),
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.phy_tx_rst(phy_1_tx_rst),
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.phy_xgmii_txd(phy_1_xgmii_txd),
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.phy_xgmii_txc(phy_1_xgmii_txc),
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.phy_rx_clk(phy_1_rx_clk),
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.phy_rx_rst(phy_1_rx_rst),
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.phy_xgmii_rxd(phy_1_xgmii_rxd),
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.phy_xgmii_rxc(phy_1_xgmii_rxc),
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.phy_tx_bad_block(phy_1_tx_bad_block),
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.phy_rx_error_count(phy_1_rx_error_count),
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.phy_rx_bad_block(phy_1_rx_bad_block),
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.phy_rx_sequence_error(phy_1_rx_sequence_error),
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.phy_rx_block_lock(phy_1_rx_block_lock),
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.phy_rx_high_ber(phy_1_rx_high_ber),
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.phy_rx_status(phy_1_rx_status),
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.phy_cfg_tx_prbs31_enable(phy_1_cfg_tx_prbs31_enable),
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.phy_cfg_rx_prbs31_enable(phy_1_cfg_rx_prbs31_enable)
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);
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end
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if (COUNT > 1) begin : phy2
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eth_xcvr_phy_wrapper #(
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.HAS_COMMON(0),
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.DATA_WIDTH(DATA_WIDTH),
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.CTRL_WIDTH(CTRL_WIDTH),
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.HDR_WIDTH(HDR_WIDTH),
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.PRBS31_ENABLE(PRBS31_ENABLE),
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.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
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.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
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.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
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.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
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.COUNT_125US(COUNT_125US)
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)
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eth_xcvr_phy_2 (
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.xcvr_ctrl_clk(xcvr_ctrl_clk),
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.xcvr_ctrl_rst(xcvr_ctrl_rst),
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// Common
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.xcvr_gtpowergood_out(),
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// PLL out
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.xcvr_gtrefclk00_in(1'b0),
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.xcvr_qpll0lock_out(),
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.xcvr_qpll0clk_out(),
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.xcvr_qpll0refclk_out(),
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// PLL in
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.xcvr_qpll0lock_in(xcvr_qpll0lock),
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.xcvr_qpll0clk_in(xcvr_qpll0clk),
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.xcvr_qpll0refclk_in(xcvr_qpll0refclk),
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// Serial data
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.xcvr_txp(xcvr_txp[1]),
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.xcvr_txn(xcvr_txn[1]),
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.xcvr_rxp(xcvr_rxp[1]),
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.xcvr_rxn(xcvr_rxn[1]),
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// PHY connections
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.phy_tx_clk(phy_2_tx_clk),
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.phy_tx_rst(phy_2_tx_rst),
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.phy_xgmii_txd(phy_2_xgmii_txd),
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.phy_xgmii_txc(phy_2_xgmii_txc),
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.phy_rx_clk(phy_2_rx_clk),
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.phy_rx_rst(phy_2_rx_rst),
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.phy_xgmii_rxd(phy_2_xgmii_rxd),
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.phy_xgmii_rxc(phy_2_xgmii_rxc),
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.phy_tx_bad_block(phy_2_tx_bad_block),
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.phy_rx_error_count(phy_2_rx_error_count),
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.phy_rx_bad_block(phy_2_rx_bad_block),
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.phy_rx_sequence_error(phy_2_rx_sequence_error),
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.phy_rx_block_lock(phy_2_rx_block_lock),
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.phy_rx_high_ber(phy_2_rx_high_ber),
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.phy_rx_status(phy_2_rx_status),
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.phy_cfg_tx_prbs31_enable(phy_2_cfg_tx_prbs31_enable),
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.phy_cfg_rx_prbs31_enable(phy_2_cfg_rx_prbs31_enable)
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);
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end
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if (COUNT > 2) begin : phy3
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eth_xcvr_phy_wrapper #(
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.HAS_COMMON(0),
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.DATA_WIDTH(DATA_WIDTH),
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.CTRL_WIDTH(CTRL_WIDTH),
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.HDR_WIDTH(HDR_WIDTH),
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.PRBS31_ENABLE(PRBS31_ENABLE),
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.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
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.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
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.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
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.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
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.COUNT_125US(COUNT_125US)
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)
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eth_xcvr_phy_3 (
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.xcvr_ctrl_clk(xcvr_ctrl_clk),
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.xcvr_ctrl_rst(xcvr_ctrl_rst),
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// Common
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.xcvr_gtpowergood_out(),
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// PLL out
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.xcvr_gtrefclk00_in(1'b0),
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.xcvr_qpll0lock_out(),
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.xcvr_qpll0clk_out(),
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.xcvr_qpll0refclk_out(),
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// PLL in
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.xcvr_qpll0lock_in(xcvr_qpll0lock),
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.xcvr_qpll0clk_in(xcvr_qpll0clk),
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.xcvr_qpll0refclk_in(xcvr_qpll0refclk),
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// Serial data
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.xcvr_txp(xcvr_txp[2]),
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.xcvr_txn(xcvr_txn[2]),
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.xcvr_rxp(xcvr_rxp[2]),
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.xcvr_rxn(xcvr_rxn[2]),
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// PHY connections
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.phy_tx_clk(phy_3_tx_clk),
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.phy_tx_rst(phy_3_tx_rst),
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.phy_xgmii_txd(phy_3_xgmii_txd),
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.phy_xgmii_txc(phy_3_xgmii_txc),
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.phy_rx_clk(phy_3_rx_clk),
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.phy_rx_rst(phy_3_rx_rst),
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.phy_xgmii_rxd(phy_3_xgmii_rxd),
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.phy_xgmii_rxc(phy_3_xgmii_rxc),
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.phy_tx_bad_block(phy_3_tx_bad_block),
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.phy_rx_error_count(phy_3_rx_error_count),
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.phy_rx_bad_block(phy_3_rx_bad_block),
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.phy_rx_sequence_error(phy_3_rx_sequence_error),
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.phy_rx_block_lock(phy_3_rx_block_lock),
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.phy_rx_high_ber(phy_3_rx_high_ber),
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.phy_rx_status(phy_3_rx_status),
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.phy_cfg_tx_prbs31_enable(phy_3_cfg_tx_prbs31_enable),
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.phy_cfg_rx_prbs31_enable(phy_3_cfg_rx_prbs31_enable)
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);
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end
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if (COUNT > 3) begin : phy4
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eth_xcvr_phy_wrapper #(
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.HAS_COMMON(0),
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.DATA_WIDTH(DATA_WIDTH),
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.CTRL_WIDTH(CTRL_WIDTH),
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.HDR_WIDTH(HDR_WIDTH),
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.PRBS31_ENABLE(PRBS31_ENABLE),
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.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
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.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
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.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
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.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
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.COUNT_125US(COUNT_125US)
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)
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eth_xcvr_phy_4 (
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.xcvr_ctrl_clk(xcvr_ctrl_clk),
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.xcvr_ctrl_rst(xcvr_ctrl_rst),
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// Common
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.xcvr_gtpowergood_out(),
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// PLL out
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.xcvr_gtrefclk00_in(1'b0),
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.xcvr_qpll0lock_out(),
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.xcvr_qpll0clk_out(),
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.xcvr_qpll0refclk_out(),
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// PLL in
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.xcvr_qpll0lock_in(xcvr_qpll0lock),
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.xcvr_qpll0clk_in(xcvr_qpll0clk),
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.xcvr_qpll0refclk_in(xcvr_qpll0refclk),
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// Serial data
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.xcvr_txp(xcvr_txp[3]),
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.xcvr_txn(xcvr_txn[3]),
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.xcvr_rxp(xcvr_rxp[3]),
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.xcvr_rxn(xcvr_rxn[3]),
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// PHY connections
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.phy_tx_clk(phy_4_tx_clk),
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.phy_tx_rst(phy_4_tx_rst),
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.phy_xgmii_txd(phy_4_xgmii_txd),
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.phy_xgmii_txc(phy_4_xgmii_txc),
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.phy_rx_clk(phy_4_rx_clk),
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.phy_rx_rst(phy_4_rx_rst),
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.phy_xgmii_rxd(phy_4_xgmii_rxd),
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.phy_xgmii_rxc(phy_4_xgmii_rxc),
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.phy_tx_bad_block(phy_4_tx_bad_block),
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.phy_rx_error_count(phy_4_rx_error_count),
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.phy_rx_bad_block(phy_4_rx_bad_block),
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.phy_rx_sequence_error(phy_4_rx_sequence_error),
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.phy_rx_block_lock(phy_4_rx_block_lock),
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.phy_rx_high_ber(phy_4_rx_high_ber),
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.phy_rx_status(phy_4_rx_status),
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.phy_cfg_tx_prbs31_enable(phy_4_cfg_tx_prbs31_enable),
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.phy_cfg_rx_prbs31_enable(phy_4_cfg_rx_prbs31_enable)
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);
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end
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endgenerate
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endmodule
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`resetall
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