mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-28 07:03:08 +08:00
460 lines
13 KiB
Python
460 lines
13 KiB
Python
#!/usr/bin/env python
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"""
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Copyright (c) 2020-2023 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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import logging
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import os
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from statistics import mean, stdev
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import pytest
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import cocotb_test.simulator
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import RisingEdge, Timer
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from cocotb.utils import get_sim_steps, get_sim_time
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from cocotbext.eth import PtpClock
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class TB:
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def __init__(self, dut):
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self.dut = dut
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self.log = logging.getLogger("cocotb.tb")
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self.log.setLevel(logging.DEBUG)
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cocotb.start_soon(Clock(dut.sample_clk, 9.9, units="ns").start())
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if len(dut.input_ts) == 64:
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self.ptp_clock = PtpClock(
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ts_rel=dut.input_ts,
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ts_step=dut.input_ts_step,
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clock=dut.input_clk,
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reset=dut.input_rst,
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period_ns=6.4
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)
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else:
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self.ptp_clock = PtpClock(
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ts_tod=dut.input_ts,
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ts_step=dut.input_ts_step,
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clock=dut.input_clk,
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reset=dut.input_rst,
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period_ns=6.4
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)
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self.input_clock_period = 6.4
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dut.input_clk.setimmediatevalue(0)
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cocotb.start_soon(self._run_input_clock())
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self.output_clock_period = 6.4
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dut.output_clk.setimmediatevalue(0)
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cocotb.start_soon(self._run_output_clock())
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async def reset(self):
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self.dut.input_rst.setimmediatevalue(0)
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self.dut.output_rst.setimmediatevalue(0)
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await RisingEdge(self.dut.input_clk)
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await RisingEdge(self.dut.input_clk)
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self.dut.input_rst.value = 1
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self.dut.output_rst.value = 1
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for k in range(10):
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await RisingEdge(self.dut.input_clk)
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self.dut.input_rst.value = 0
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self.dut.output_rst.value = 0
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for k in range(10):
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await RisingEdge(self.dut.input_clk)
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def set_input_clock_period(self, period):
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self.input_clock_period = period
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async def _run_input_clock(self):
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period = None
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steps_per_ns = get_sim_steps(1.0, 'ns')
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while True:
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if period != self.input_clock_period:
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period = self.input_clock_period
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t = Timer(int(steps_per_ns * period / 2.0))
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await t
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self.dut.input_clk.value = 1
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await t
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self.dut.input_clk.value = 0
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def set_output_clock_period(self, period):
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self.output_clock_period = period
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async def _run_output_clock(self):
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period = None
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steps_per_ns = get_sim_steps(1.0, 'ns')
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while True:
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if period != self.output_clock_period:
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period = self.output_clock_period
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t = Timer(int(steps_per_ns * period / 2.0))
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await t
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self.dut.output_clk.value = 1
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await t
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self.dut.output_clk.value = 0
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def get_input_ts_ns(self):
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ts = self.dut.input_ts.value.integer
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if len(self.dut.input_ts) == 64:
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return ts/2**16*1e-9
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else:
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return (ts >> 48) + ((ts & 0xffffffffffff)/2**16*1e-9)
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def get_output_ts_ns(self):
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ts = self.dut.output_ts.value.integer
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if len(self.dut.output_ts) == 64:
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return ts/2**16*1e-9
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else:
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return (ts >> 48) + ((ts & 0xffffffffffff)/2**16*1e-9)
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async def measure_ts_diff(self, N=100):
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input_ts_lst = []
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output_ts_lst = []
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async def collect_timestamps(clk, get_ts, lst):
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while True:
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await RisingEdge(clk)
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lst.append((get_sim_time('sec'), get_ts()))
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input_cr = cocotb.start_soon(collect_timestamps(self.dut.input_clk, self.get_input_ts_ns, input_ts_lst))
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output_cr = cocotb.start_soon(collect_timestamps(self.dut.output_clk, self.get_output_ts_ns, output_ts_lst))
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for k in range(N):
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await RisingEdge(self.dut.output_clk)
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input_cr.kill()
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output_cr.kill()
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diffs = []
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its1 = input_ts_lst.pop(0)
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its2 = input_ts_lst.pop(0)
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for ots in output_ts_lst:
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while its2[0] < ots[0] and input_ts_lst:
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its1 = its2
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its2 = input_ts_lst.pop(0)
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if its2[0] < ots[0]:
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break
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dt = its2[0] - its1[0]
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dts = its2[1] - its1[1]
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its = its1[1]+dts/dt*(ots[0]-its1[0])
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diffs.append(ots[1] - its)
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return diffs
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@cocotb.test()
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async def run_test(dut):
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tb = TB(dut)
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await tb.reset()
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await RisingEdge(dut.input_clk)
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tb.log.info("Same clock speed")
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tb.set_input_clock_period(6.4)
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tb.set_output_clock_period(6.4)
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await RisingEdge(dut.input_clk)
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for i in range(100000):
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await RisingEdge(dut.input_clk)
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assert tb.dut.locked.value.integer
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diffs = await tb.measure_ts_diff()
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tb.log.info(f"Difference: {mean(diffs)*1e9} ns (stdev: {stdev(diffs)*1e9})")
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assert abs(mean(diffs)*1e9) < 5
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await RisingEdge(dut.input_clk)
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tb.log.info("10 ppm slower")
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tb.set_input_clock_period(6.4)
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tb.set_output_clock_period(6.4*(1+.00001))
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await RisingEdge(dut.input_clk)
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for i in range(100000):
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await RisingEdge(dut.input_clk)
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assert tb.dut.locked.value.integer
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diffs = await tb.measure_ts_diff()
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tb.log.info(f"Difference: {mean(diffs)*1e9} ns (stdev: {stdev(diffs)*1e9})")
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assert abs(mean(diffs)*1e9) < 5
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await RisingEdge(dut.input_clk)
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tb.log.info("10 ppm faster")
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tb.set_input_clock_period(6.4)
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tb.set_output_clock_period(6.4*(1-.00001))
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await RisingEdge(dut.input_clk)
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for i in range(100000):
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await RisingEdge(dut.input_clk)
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assert tb.dut.locked.value.integer
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diffs = await tb.measure_ts_diff()
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tb.log.info(f"Difference: {mean(diffs)*1e9} ns (stdev: {stdev(diffs)*1e9})")
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assert abs(mean(diffs)*1e9) < 5
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await RisingEdge(dut.input_clk)
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tb.log.info("200 ppm slower")
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tb.set_input_clock_period(6.4)
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tb.set_output_clock_period(6.4*(1+.0002))
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await RisingEdge(dut.input_clk)
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for i in range(100000):
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await RisingEdge(dut.input_clk)
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assert tb.dut.locked.value.integer
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diffs = await tb.measure_ts_diff()
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tb.log.info(f"Difference: {mean(diffs)*1e9} ns (stdev: {stdev(diffs)*1e9})")
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assert abs(mean(diffs)*1e9) < 5
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await RisingEdge(dut.input_clk)
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tb.log.info("200 ppm faster")
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tb.set_input_clock_period(6.4)
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tb.set_output_clock_period(6.4*(1-.0002))
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await RisingEdge(dut.input_clk)
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for i in range(100000):
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await RisingEdge(dut.input_clk)
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assert tb.dut.locked.value.integer
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diffs = await tb.measure_ts_diff()
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tb.log.info(f"Difference: {mean(diffs)*1e9} ns (stdev: {stdev(diffs)*1e9})")
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assert abs(mean(diffs)*1e9) < 5
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await RisingEdge(dut.input_clk)
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tb.log.info("Coherent tracking (+/- 10 ppm)")
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tb.set_input_clock_period(6.4)
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tb.set_output_clock_period(6.4)
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await RisingEdge(dut.input_clk)
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period = 6.400
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step = 0.000002
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period_min = 6.4*(1-.00001)
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period_max = 6.4*(1+.00001)
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for i in range(500):
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period += step
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if period <= period_min:
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step = abs(step)
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if period >= period_max:
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step = -abs(step)
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tb.set_output_clock_period(period)
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for i in range(200):
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await RisingEdge(dut.input_clk)
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assert tb.dut.locked.value.integer
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diffs = await tb.measure_ts_diff()
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tb.log.info(f"Difference: {mean(diffs)*1e9} ns (stdev: {stdev(diffs)*1e9})")
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assert abs(mean(diffs)*1e9) < 5
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await RisingEdge(dut.input_clk)
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tb.log.info("Coherent tracking (+/- 200 ppm)")
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tb.set_input_clock_period(6.4)
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tb.set_output_clock_period(6.4)
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await RisingEdge(dut.input_clk)
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period = 6.400
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step = 0.000002
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period_min = 6.4*(1-.0002)
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period_max = 6.4*(1+.0002)
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for i in range(5000):
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period += step
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if period <= period_min:
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step = abs(step)
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if period >= period_max:
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step = -abs(step)
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tb.set_output_clock_period(period)
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for i in range(20):
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await RisingEdge(dut.input_clk)
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assert tb.dut.locked.value.integer
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diffs = await tb.measure_ts_diff()
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tb.log.info(f"Difference: {mean(diffs)*1e9} ns (stdev: {stdev(diffs)*1e9})")
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assert abs(mean(diffs)*1e9) < 5
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await RisingEdge(dut.input_clk)
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tb.log.info("Slightly faster (6.3 ns)")
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tb.set_input_clock_period(6.4)
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tb.set_output_clock_period(6.3)
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await RisingEdge(dut.input_clk)
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for i in range(100000):
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await RisingEdge(dut.input_clk)
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assert tb.dut.locked.value.integer
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diffs = await tb.measure_ts_diff()
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tb.log.info(f"Difference: {mean(diffs)*1e9} ns (stdev: {stdev(diffs)*1e9})")
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assert abs(mean(diffs)*1e9) < 5
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await RisingEdge(dut.input_clk)
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tb.log.info("Slightly slower (6.5 ns)")
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tb.set_input_clock_period(6.4)
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tb.set_output_clock_period(6.5)
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await RisingEdge(dut.input_clk)
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for i in range(100000):
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await RisingEdge(dut.input_clk)
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assert tb.dut.locked.value.integer
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diffs = await tb.measure_ts_diff()
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tb.log.info(f"Difference: {mean(diffs)*1e9} ns (stdev: {stdev(diffs)*1e9})")
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assert abs(mean(diffs)*1e9) < 5
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await RisingEdge(dut.input_clk)
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tb.log.info("Significantly faster (250 MHz)")
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tb.set_input_clock_period(6.4)
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tb.set_output_clock_period(4.0)
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await RisingEdge(dut.input_clk)
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for i in range(100000):
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await RisingEdge(dut.input_clk)
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assert tb.dut.locked.value.integer
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diffs = await tb.measure_ts_diff()
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tb.log.info(f"Difference: {mean(diffs)*1e9} ns (stdev: {stdev(diffs)*1e9})")
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assert abs(mean(diffs)*1e9) < 5
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await RisingEdge(dut.input_clk)
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tb.log.info("Significantly slower (100 MHz)")
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tb.set_input_clock_period(6.4)
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tb.set_output_clock_period(10.0)
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await RisingEdge(dut.input_clk)
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for i in range(100000):
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await RisingEdge(dut.input_clk)
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assert tb.dut.locked.value.integer
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diffs = await tb.measure_ts_diff()
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tb.log.info(f"Difference: {mean(diffs)*1e9} ns (stdev: {stdev(diffs)*1e9})")
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assert abs(mean(diffs)*1e9) < 5
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await RisingEdge(dut.input_clk)
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tb.log.info("Significantly faster (390.625 MHz)")
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tb.set_input_clock_period(6.4)
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tb.set_output_clock_period(2.56)
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await RisingEdge(dut.input_clk)
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for i in range(100000):
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await RisingEdge(dut.input_clk)
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assert tb.dut.locked.value.integer
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diffs = await tb.measure_ts_diff()
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tb.log.info(f"Difference: {mean(diffs)*1e9} ns (stdev: {stdev(diffs)*1e9})")
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assert abs(mean(diffs)*1e9) < 5
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await RisingEdge(dut.input_clk)
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await RisingEdge(dut.input_clk)
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# cocotb-test
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tests_dir = os.path.abspath(os.path.dirname(__file__))
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rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
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lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib'))
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axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl'))
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@pytest.mark.parametrize("ts_width", [96, 64])
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def test_ptp_clock_cdc(request, ts_width):
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dut = "ptp_clock_cdc"
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module = os.path.splitext(os.path.basename(__file__))[0]
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toplevel = dut
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verilog_sources = [
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os.path.join(rtl_dir, f"{dut}.v"),
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]
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parameters = {}
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parameters['TS_WIDTH'] = ts_width
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parameters['NS_WIDTH'] = 4
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parameters['LOG_RATE'] = 3
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parameters['PIPELINE_OUTPUT'] = 0
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extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
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sim_build = os.path.join(tests_dir, "sim_build",
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request.node.name.replace('[', '-').replace(']', ''))
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cocotb_test.simulator.run(
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python_search=[tests_dir],
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verilog_sources=verilog_sources,
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toplevel=toplevel,
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module=module,
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parameters=parameters,
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sim_build=sim_build,
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extra_env=extra_env,
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)
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