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verilog-ethernet/tb/axis_baser_rx_64
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Alex Forencich fa05d4ff3c Add TX and RX enable inputs to MACs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-08-24 01:24:33 -07:00
..
baser.py
Add cocotb testbenches for AXI stream BASE-R TX and RX modules
2021-10-15 01:08:14 -07:00
Makefile
Remove recursively-expanded macros for module parameters in makefiles
2023-02-17 16:04:16 -08:00
test_axis_baser_rx_64.py
Add TX and RX enable inputs to MACs
2023-08-24 01:24:33 -07:00