Alex Forencich fd7f65d5ad Convert generated switch to verilog parametrized switch

2018-10-24 16:12:56 -07:00

..

arbiter.v

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axis_adapter.v

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axis_arb_mux.v

Convert arbitrated mux to verilog parametrized arbitrated mux

2018-10-24 13:49:17 -07:00

axis_async_fifo.v

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axis_async_frame_fifo.v

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axis_cobs_decode.v

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axis_cobs_encode.v

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axis_crosspoint.v

Convert generated crosspoint to verilog parametrized crosspoint

2018-10-24 13:44:39 -07:00

axis_demux_4.v

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axis_demux.py

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axis_fifo.v

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axis_frame_fifo.v

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axis_frame_join_4.v

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axis_frame_join.py

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axis_frame_length_adjust_fifo.v

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axis_frame_length_adjust.v

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axis_ll_bridge.v

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axis_mux_4.v

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axis_mux.py

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2018-02-27 01:39:25 -08:00

axis_rate_limit.v

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2018-02-26 12:25:20 -08:00

axis_register.v

Rename ports and add reg_type parameter to axis_register

2018-10-24 14:35:08 -07:00

axis_srl_fifo.v

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2018-02-26 12:25:20 -08:00

axis_srl_register.v

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axis_stat_counter.v

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2018-02-26 12:25:20 -08:00

axis_switch.v

Convert generated switch to verilog parametrized switch

2018-10-24 16:12:56 -07:00

axis_tap.v

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2018-02-26 12:25:20 -08:00

ll_axis_bridge.v

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2018-02-26 12:25:20 -08:00

priority_encoder.v

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2018-02-26 12:25:20 -08:00