321 lines
11 KiB
Python
321 lines
11 KiB
Python
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#!/usr/bin/env python
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"""
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Copyright (c) 2019 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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from myhdl import *
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import os
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import dma_ram
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import axis_ep
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module = 'dma_client_axis_sink'
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testbench = 'test_%s_128_64' % module
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srcs = []
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srcs.append("../rtl/%s.v" % module)
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srcs.append("%s.v" % testbench)
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src = ' '.join(srcs)
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build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
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def bench():
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# Parameters
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SEG_COUNT = 2
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SEG_DATA_WIDTH = 64
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SEG_ADDR_WIDTH = 12
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SEG_BE_WIDTH = int(SEG_DATA_WIDTH/8)
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RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+SEG_COUNT.bit_length()+SEG_BE_WIDTH.bit_length()
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AXIS_DATA_WIDTH = SEG_DATA_WIDTH*SEG_COUNT/2
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AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8)
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AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8)
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AXIS_LAST_ENABLE = 1
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AXIS_ID_ENABLE = 0
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AXIS_ID_WIDTH = 8
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AXIS_DEST_ENABLE = 0
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AXIS_DEST_WIDTH = 8
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AXIS_USER_ENABLE = 1
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AXIS_USER_WIDTH = 1
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LEN_WIDTH = 20
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TAG_WIDTH = 8
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# Inputs
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clk = Signal(bool(0))
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rst = Signal(bool(0))
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current_test = Signal(intbv(0)[8:])
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s_axis_write_desc_ram_addr = Signal(intbv(0)[RAM_ADDR_WIDTH:])
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s_axis_write_desc_len = Signal(intbv(0)[LEN_WIDTH:])
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s_axis_write_desc_tag = Signal(intbv(0)[TAG_WIDTH:])
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s_axis_write_desc_valid = Signal(bool(0))
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s_axis_write_data_tdata = Signal(intbv(0)[AXIS_DATA_WIDTH:])
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s_axis_write_data_tkeep = Signal(intbv(0)[AXIS_KEEP_WIDTH:])
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s_axis_write_data_tvalid = Signal(bool(0))
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s_axis_write_data_tlast = Signal(bool(0))
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s_axis_write_data_tid = Signal(intbv(0)[AXIS_ID_WIDTH:])
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s_axis_write_data_tdest = Signal(intbv(0)[AXIS_DEST_WIDTH:])
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s_axis_write_data_tuser = Signal(intbv(0)[AXIS_USER_WIDTH:])
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ram_wr_cmd_ready = Signal(intbv(0)[SEG_COUNT:])
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enable = Signal(bool(0))
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abort = Signal(bool(0))
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# Outputs
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s_axis_write_desc_ready = Signal(bool(0))
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m_axis_write_desc_status_len = Signal(intbv(0)[LEN_WIDTH:])
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m_axis_write_desc_status_tag = Signal(intbv(0)[TAG_WIDTH:])
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m_axis_write_desc_status_id = Signal(intbv(0)[AXIS_ID_WIDTH:])
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m_axis_write_desc_status_dest = Signal(intbv(0)[AXIS_DEST_WIDTH:])
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m_axis_write_desc_status_user = Signal(intbv(0)[AXIS_USER_WIDTH:])
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m_axis_write_desc_status_valid = Signal(bool(0))
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s_axis_write_data_tready = Signal(bool(0))
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ram_wr_cmd_be = Signal(intbv(0)[SEG_COUNT*SEG_BE_WIDTH:])
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ram_wr_cmd_addr = Signal(intbv(0)[SEG_COUNT*SEG_ADDR_WIDTH:])
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ram_wr_cmd_data = Signal(intbv(0)[SEG_COUNT*SEG_DATA_WIDTH:])
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ram_wr_cmd_valid = Signal(intbv(0)[SEG_COUNT:])
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# PCIe DMA RAM
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dma_ram_inst = dma_ram.PSDPRam(2**16)
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dma_ram_pause = Signal(bool(0))
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dma_ram_port0 = dma_ram_inst.create_write_ports(
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clk,
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ram_wr_cmd_be=ram_wr_cmd_be,
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ram_wr_cmd_addr=ram_wr_cmd_addr,
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ram_wr_cmd_data=ram_wr_cmd_data,
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ram_wr_cmd_valid=ram_wr_cmd_valid,
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ram_wr_cmd_ready=ram_wr_cmd_ready,
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pause=dma_ram_pause,
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name='port0'
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)
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# sources and sinks
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write_desc_source = axis_ep.AXIStreamSource()
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write_desc_source_pause = Signal(bool(False))
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write_desc_source_logic = write_desc_source.create_logic(
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clk,
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rst,
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tdata=(s_axis_write_desc_ram_addr, s_axis_write_desc_len, s_axis_write_desc_tag),
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tvalid=s_axis_write_desc_valid,
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tready=s_axis_write_desc_ready,
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pause=write_desc_source_pause,
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name='write_desc_source'
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)
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write_desc_status_sink = axis_ep.AXIStreamSink()
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write_desc_status_sink_logic = write_desc_status_sink.create_logic(
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clk,
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rst,
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tdata=(m_axis_write_desc_status_len, m_axis_write_desc_status_tag, m_axis_write_desc_status_id, m_axis_write_desc_status_dest, m_axis_write_desc_status_user),
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tvalid=m_axis_write_desc_status_valid,
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name='write_desc_status_sink'
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)
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write_data_source = axis_ep.AXIStreamSource()
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write_data_source_pause = Signal(bool(False))
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write_data_source_logic = write_data_source.create_logic(
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clk,
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rst,
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tdata=s_axis_write_data_tdata,
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tkeep=s_axis_write_data_tkeep,
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tvalid=s_axis_write_data_tvalid,
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tready=s_axis_write_data_tready,
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tlast=s_axis_write_data_tlast,
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tid=s_axis_write_data_tid,
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tdest=s_axis_write_data_tdest,
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tuser=s_axis_write_data_tuser,
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pause=write_data_source_pause,
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name='write_data_source'
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)
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# DUT
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if os.system(build_cmd):
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raise Exception("Error running build command")
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dut = Cosimulation(
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"vvp -m myhdl %s.vvp -lxt2" % testbench,
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clk=clk,
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rst=rst,
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current_test=current_test,
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s_axis_write_desc_ram_addr=s_axis_write_desc_ram_addr,
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s_axis_write_desc_len=s_axis_write_desc_len,
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s_axis_write_desc_tag=s_axis_write_desc_tag,
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s_axis_write_desc_valid=s_axis_write_desc_valid,
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s_axis_write_desc_ready=s_axis_write_desc_ready,
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m_axis_write_desc_status_len=m_axis_write_desc_status_len,
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m_axis_write_desc_status_tag=m_axis_write_desc_status_tag,
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m_axis_write_desc_status_id=m_axis_write_desc_status_id,
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m_axis_write_desc_status_dest=m_axis_write_desc_status_dest,
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m_axis_write_desc_status_user=m_axis_write_desc_status_user,
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m_axis_write_desc_status_valid=m_axis_write_desc_status_valid,
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s_axis_write_data_tdata=s_axis_write_data_tdata,
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s_axis_write_data_tkeep=s_axis_write_data_tkeep,
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s_axis_write_data_tvalid=s_axis_write_data_tvalid,
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s_axis_write_data_tready=s_axis_write_data_tready,
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s_axis_write_data_tlast=s_axis_write_data_tlast,
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s_axis_write_data_tid=s_axis_write_data_tid,
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s_axis_write_data_tdest=s_axis_write_data_tdest,
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s_axis_write_data_tuser=s_axis_write_data_tuser,
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ram_wr_cmd_be=ram_wr_cmd_be,
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ram_wr_cmd_addr=ram_wr_cmd_addr,
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ram_wr_cmd_data=ram_wr_cmd_data,
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ram_wr_cmd_valid=ram_wr_cmd_valid,
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ram_wr_cmd_ready=ram_wr_cmd_ready,
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enable=enable,
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abort=abort
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)
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@always(delay(4))
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def clkgen():
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clk.next = not clk
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def wait_normal():
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while write_desc_status_sink.empty():
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yield clk.posedge
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def wait_pause_ram():
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while write_desc_status_sink.empty():
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dma_ram_pause.next = True
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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dma_ram_pause.next = False
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yield clk.posedge
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def wait_pause_source():
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while write_desc_status_sink.empty():
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write_data_source_pause.next = True
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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write_data_source_pause.next = False
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yield clk.posedge
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@instance
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def check():
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yield delay(100)
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yield clk.posedge
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rst.next = 1
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yield clk.posedge
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rst.next = 0
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yield clk.posedge
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yield delay(100)
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yield clk.posedge
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# testbench stimulus
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cur_tag = 1
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enable.next = 1
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yield clk.posedge
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print("test 1: write")
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current_test.next = 1
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addr = 0x00000000
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test_data = b'\x11\x22\x33\x44'
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write_desc_source.send([(addr, len(test_data), cur_tag)])
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write_data_source.send(axis_ep.AXIStreamFrame(test_data, id=cur_tag))
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yield write_desc_status_sink.wait(2000)
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status = write_desc_status_sink.recv()
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print(status)
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assert status.data[0][0] == len(test_data)
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assert status.data[0][1] == cur_tag
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assert status.data[0][2] == cur_tag
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data = dma_ram_inst.read_mem(addr, 32)
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for i in range(0, len(data), 16):
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print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
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assert dma_ram_inst.read_mem(addr, len(test_data)) == test_data
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cur_tag = (cur_tag + 1) % 256
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yield delay(100)
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yield clk.posedge
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print("test 2: various writes")
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current_test.next = 2
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for length in list(range(1,34))+[128]:
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for offset in list(range(8,17,8))+list(range(4096-8,4096,8)):
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for diff in [-16, -2, -1, 0, 1, 2, 16]:
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if length+diff < 1:
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continue
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for wait in wait_normal, wait_pause_ram, wait_pause_source:
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print("length %d, offset %d, diff %d"% (length, offset, diff))
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#addr = length * 0x100000000 + offset * 0x10000 + offset
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addr = offset
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test_data = bytearray([x%256 for x in range(length)])
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test_data2 = bytearray([x%256 for x in range(length+diff)])
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dma_ram_inst.write_mem(addr & 0xffff80, b'\xaa'*(len(test_data)+256))
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write_desc_source.send([(addr, len(test_data), cur_tag)])
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write_data_source.send(axis_ep.AXIStreamFrame(test_data2, id=cur_tag))
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yield wait()
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yield clk.posedge
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yield clk.posedge
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status = write_desc_status_sink.recv()
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print(status)
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assert status.data[0][0] == min(len(test_data), len(test_data2))
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assert status.data[0][1] == cur_tag
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assert status.data[0][2] == cur_tag
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data = dma_ram_inst.read_mem(addr&0xfffff0, 64)
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for i in range(0, len(data), 16):
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print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
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if len(test_data) <= len(test_data2):
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assert dma_ram_inst.read_mem(addr-8, len(test_data)+16) == b'\xaa'*8+test_data+b'\xaa'*8
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else:
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assert dma_ram_inst.read_mem(addr-8, len(test_data2)+16) == b'\xaa'*8+test_data2+b'\xaa'*8
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cur_tag = (cur_tag + 1) % 256
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yield delay(100)
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raise StopSimulation
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return instances()
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def test_bench():
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sim = Simulation(bench())
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sim.run()
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if __name__ == '__main__':
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print("Running test...")
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test_bench()
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