Add priority encoder and arbiter modules
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Alex Forencich
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153
rtl/arbiter.v
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153
rtl/arbiter.v
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/*
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Copyright (c) 2014-2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* Arbiter module
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*/
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module arbiter #
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(
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parameter PORTS = 4,
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// arbitration type: "PRIORITY" or "ROUND_ROBIN"
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parameter TYPE = "PRIORITY",
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// block type: "NONE", "REQUEST", "ACKNOWLEDGE"
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parameter BLOCK = "NONE",
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// LSB priority: "LOW", "HIGH"
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parameter LSB_PRIORITY = "LOW"
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)
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(
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input wire clk,
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input wire rst,
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input wire [PORTS-1:0] request,
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input wire [PORTS-1:0] acknowledge,
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output wire [PORTS-1:0] grant,
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output wire grant_valid,
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output wire [$clog2(PORTS)-1:0] grant_encoded
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);
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reg [PORTS-1:0] grant_reg = 0, grant_next;
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reg grant_valid_reg = 0, grant_valid_next;
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reg [$clog2(PORTS)-1:0] grant_encoded_reg = 0, grant_encoded_next;
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assign grant_valid = grant_valid_reg;
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assign grant = grant_reg;
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assign grant_encoded = grant_encoded_reg;
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wire request_valid;
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wire [$clog2(PORTS)-1:0] request_index;
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wire [PORTS-1:0] request_mask;
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priority_encoder #(
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.WIDTH(PORTS),
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.LSB_PRIORITY(LSB_PRIORITY)
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)
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priority_encoder_inst (
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.input_unencoded(request),
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.output_valid(request_valid),
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.output_encoded(request_index),
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.output_unencoded(request_mask)
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);
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reg [PORTS-1:0] mask_reg = 0, mask_next;
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wire masked_request_valid;
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wire [$clog2(PORTS)-1:0] masked_request_index;
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wire [PORTS-1:0] masked_request_mask;
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priority_encoder #(
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.WIDTH(PORTS),
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.LSB_PRIORITY(LSB_PRIORITY)
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)
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priority_encoder_masked (
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.input_unencoded(request & mask_reg),
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.output_valid(masked_request_valid),
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.output_encoded(masked_request_index),
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.output_unencoded(masked_request_mask)
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);
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always @* begin
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grant_next = 0;
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grant_valid_next = 0;
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grant_encoded_next = 0;
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mask_next = mask_reg;
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if (BLOCK == "REQUEST" && grant_reg & request) begin
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// granted request still asserted; hold it
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grant_valid_next = grant_valid_reg;
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grant_next = grant_reg;
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grant_encoded_next = grant_encoded_reg;
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end else if (BLOCK == "ACKNOWLEDGE" && grant_valid && !(grant_reg & acknowledge)) begin
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// granted request not yet acknowledged; hold it
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grant_valid_next = grant_valid_reg;
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grant_next = grant_reg;
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grant_encoded_next = grant_encoded_reg;
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end else if (request_valid) begin
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if (TYPE == "PRIORITY") begin
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grant_valid_next = 1;
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grant_next = request_mask;
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grant_encoded_next = request_index;
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end else if (TYPE == "ROUND_ROBIN") begin
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if (masked_request_valid) begin
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grant_valid_next = 1;
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grant_next = masked_request_mask;
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grant_encoded_next = masked_request_index;
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if (LSB_PRIORITY == "LOW") begin
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mask_next = {PORTS{1'b1}} >> (PORTS - masked_request_index);
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end else begin
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mask_next = {PORTS{1'b1}} << (masked_request_index + 1);
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end
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end else begin
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grant_valid_next = 1;
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grant_next = request_mask;
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grant_encoded_next = request_index;
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if (LSB_PRIORITY == "LOW") begin
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mask_next = {PORTS{1'b1}} >> (PORTS - request_index);
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end else begin
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mask_next = {PORTS{1'b1}} << (request_index + 1);
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end
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end
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end
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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grant_reg <= 0;
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grant_valid_reg <= 0;
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grant_encoded_reg <= 0;
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mask_reg <= 0;
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end else begin
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grant_reg <= grant_next;
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grant_valid_reg <= grant_valid_next;
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grant_encoded_reg <= grant_encoded_next;
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mask_reg <= mask_next;
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end
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end
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endmodule
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94
rtl/priority_encoder.v
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94
rtl/priority_encoder.v
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@ -0,0 +1,94 @@
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/*
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Copyright (c) 2014-2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* Priority encoder module
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*/
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module priority_encoder #
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(
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parameter WIDTH = 4,
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// LSB priority: "LOW", "HIGH"
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parameter LSB_PRIORITY = "LOW"
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)
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(
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input wire [WIDTH-1:0] input_unencoded,
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output wire output_valid,
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output wire [$clog2(WIDTH)-1:0] output_encoded,
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output wire [WIDTH-1:0] output_unencoded
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);
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// power-of-two width
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parameter W1 = 2**$clog2(WIDTH);
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parameter W2 = W1/2;
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generate
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if (WIDTH == 2) begin
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// two inputs - just an OR gate
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assign output_valid = |input_unencoded;
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if (LSB_PRIORITY == "LOW") begin
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assign output_encoded = input_unencoded[1];
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end else begin
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assign output_encoded = ~input_unencoded[0];
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end
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end else begin
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// more than two inputs - split into two parts and recurse
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// also pad input to correct power-of-two width
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wire [$clog2(W2)-1:0] out1, out2;
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wire valid1, valid2;
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priority_encoder #(
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.WIDTH(W2),
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.LSB_PRIORITY(LSB_PRIORITY)
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)
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priority_encoder_inst1 (
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.input_unencoded(input_unencoded[W2-1:0]),
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.output_valid(valid1),
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.output_encoded(out1)
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);
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priority_encoder #(
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.WIDTH(W2),
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.LSB_PRIORITY(LSB_PRIORITY)
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)
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priority_encoder_inst2 (
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.input_unencoded({{W1-WIDTH{1'b0}}, input_unencoded[WIDTH-1:W2]}),
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.output_valid(valid2),
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.output_encoded(out2)
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);
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// multiplexer to select part
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assign output_valid = valid1 | valid2;
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if (LSB_PRIORITY == "LOW") begin
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assign output_encoded = valid2 ? {1'b1, out2} : {1'b0, out1};
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end else begin
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assign output_encoded = valid1 ? {1'b0, out1} : {1'b1, out2};
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end
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end
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endgenerate
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// unencoded output
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assign output_unencoded = 1 << output_encoded;
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endmodule
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