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Sync data handling

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This commit is contained in:
Alex Forencich 2021-02-16 13:56:44 -08:00
parent 742ef1c272
commit 057a93e07a
2 changed files with 10 additions and 2 deletions
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6
rtl/dma_client_axis_sink.v
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@ -235,7 +235,11 @@ always @* begin
s_axis_write_data_tready_next = 1'b0;
ram_wr_cmd_be_int = (s_axis_write_data_tkeep & keep_mask_reg) << (addr_reg & ({PART_COUNT_WIDTH{1'b1}} << PART_OFFSET_WIDTH));
if (PART_COUNT > 1) begin
ram_wr_cmd_be_int = (s_axis_write_data_tkeep & keep_mask_reg) << (addr_reg & ({PART_COUNT_WIDTH{1'b1}} << PART_OFFSET_WIDTH));
end else begin
ram_wr_cmd_be_int = s_axis_write_data_tkeep & keep_mask_reg;
end
ram_wr_cmd_addr_int = {PART_COUNT{addr_reg[RAM_ADDR_WIDTH-1:RAM_ADDR_WIDTH-SEG_ADDR_WIDTH]}};
ram_wr_cmd_data_int = {PART_COUNT{s_axis_write_data_tdata}};
ram_wr_cmd_valid_int = {SEG_COUNT{1'b0}};

6
rtl/dma_client_axis_source.v
View File

@ -339,7 +339,11 @@ always @* begin
m_axis_read_desc_status_tag_next = m_axis_read_desc_status_tag_reg;
m_axis_read_desc_status_valid_next = 1'b0;
m_axis_read_data_tdata_int = ram_rd_resp_data >> (((addr_reg >> PART_OFFSET_WIDTH) & {PART_COUNT_WIDTH{1'b1}}) * AXIS_DATA_WIDTH);
if (PART_COUNT > 1) begin
m_axis_read_data_tdata_int = ram_rd_resp_data >> (((addr_reg >> PART_OFFSET_WIDTH) & {PART_COUNT_WIDTH{1'b1}}) * AXIS_DATA_WIDTH);
end else begin
m_axis_read_data_tdata_int = ram_rd_resp_data;
end
m_axis_read_data_tkeep_int = {AXIS_KEEP_WIDTH{1'b1}};
m_axis_read_data_tlast_int = 1'b0;
m_axis_read_data_tvalid_int = 1'b0;