FPGA/verilog-pcie
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Match IO bars for routing IO operations

Browse Source
This commit is contained in:
Alex Forencich 2019-02-15 17:23:14 -08:00
parent 35a4d62fb8
commit 13d35569fa
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
tb/pcie.py
View File

@ -2499,7 +2499,7 @@ class Bridge(Function):
pass
elif (tlp.fmt_type == TLP_IO_READ or tlp.fmt_type == TLP_IO_WRITE):
# IO read/write
if self.match_bar(tlp.address):
if self.match_bar(tlp.address, io=True):
# for me
yield from self.handle_tlp(tlp)
elif self.io_base <= tlp.address <= self.io_limit:
@ -2579,7 +2579,7 @@ class Bridge(Function):
yield from self.upstream_send(tlp)
elif (tlp.fmt_type == TLP_IO_READ or tlp.fmt_type == TLP_IO_WRITE):
# IO read/write
if self.match_bar(tlp.address):
if self.match_bar(tlp.address, io=True):
# for me
yield from self.handle_tlp(tlp)
elif self.io_base <= tlp.address <= self.io_limit: