Rewrite capability management
This commit is contained in:
Alex Forencich
parent
6baede4717
commit
1480be2173
257
tb/pcie.py
257
tb/pcie.py
@ -197,6 +197,134 @@ class PcieId(object):
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return "PcieId(%d, %d, %d)" % (self.bus, self.device, self.function)
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class PcieCap(object):
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def __init__(self, cap_id, cap_ver=None, length=None, read=None, write=None, offset=None, next_cap=None):
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self.cap_id = cap_id
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self.cap_ver = cap_ver
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self.length = length
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self.read = read
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self.write = write
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self.offset = offset
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self.next_cap = next_cap
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def read_register(self, reg):
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val = self.read(reg)
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if reg == 0:
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val = (val & 0xffff0000) | ((self.next_cap & 0xff) << 8) | (self.cap_id & 0xff)
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return val
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def write_register(self, reg, data, mask):
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self.write(reg, data, mask)
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def __repr__(self):
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return "PcieCap(cap_id={:#x}, cap_ver={}, length={}, read={}, write={}, offset={}, next_cap={})".format(self.cap_id, repr(self.cap_ver), repr(self.length), repr(self.read), repr(self.write), repr(self.offset), repr(self.next_cap))
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class PcieExtCap(PcieCap):
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def read_register(self, reg):
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if reg == 0:
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return ((self.next_cap & 0xfff) << 20) | ((self.cap_ver & 0xf) << 16) | (self.cap_id & 0xffff)
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return self.read(reg)
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class PcieCapList(object):
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def __init__(self):
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self.cap_type = PcieCap
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self.list = []
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self.start = 0x10
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self.end = 0x3f
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def find_by_id(self, cap_id):
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for cap in self.list:
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if cap.cap_id == cap_id:
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return cap
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return None
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def find_by_reg(self, reg):
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for cap in self.list:
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if cap.offset <= reg < cap.offset+cap.length:
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return cap
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return None
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def read_register(self, reg):
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cap = self.find_by_reg(reg)
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if cap:
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return cap.read_register(reg-cap.offset)
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return 0
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def write_register(self, reg, data, mask):
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cap = self.find_by_reg(reg)
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if cap:
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cap.write_register(reg-cap.offset, data, mask)
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def register(self, cap_id, cap_ver=None, length=None, read=None, write=None, offset=None):
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if isinstance(cap_id, self.cap_type):
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new_cap = cap_id
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else:
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new_cap = self.find_by_id(cap_id)
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if new_cap:
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# re-registering cap
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# remove from list
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self.list.remove(new_cap)
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# update parameters
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if cap_ver is not None:
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new_cap.cap_ver = cap_ver
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if length:
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new_cap.length = length
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if read:
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new_cap.read = read
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if write:
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new_cap.write = write
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if offset:
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new_cap.offset = offset
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if not new_cap:
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new_cap = self.cap_type(cap_id, cap_ver, length, read, write, offset)
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if not new_cap.length or not new_cap.read or not new_cap.write:
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raise Exception("Missing required parameter")
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bump_list = []
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if new_cap.offset:
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for cap in self.list:
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if cap.offset <= new_cap.offset+new_cap.length-1 and new_cap.offset <= cap.offset+cap.length-1:
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bump_list.append(cap)
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for cap in bump_list:
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self.list.remove(cap)
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else:
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new_cap.offset = self.start
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for cap in self.list:
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if cap.offset < new_cap.offset+new_cap.length-1 and new_cap.offset <= cap.offset+cap.length-1:
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new_cap.offset = cap.offset+cap.length
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self.list.append(new_cap)
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# sort list by offset
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self.list.sort(key=lambda x: x.offset)
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# update list next cap pointers
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for k in range(1, len(self.list)):
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self.list[k-1].next_cap = self.list[k].offset*4
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self.list[k].next_cap = 0
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# re-insert bumped caps
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for cap in bump_list:
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cap.offset = None
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self.register(cap)
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class PcieExtCapList(PcieCapList):
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def __init__(self):
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super(PcieExtCapList, self).__init__()
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self.cap_type = PcieExtCap
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self.start = 0x40
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self.end = 0x3ff
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class TLP(object):
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def __init__(self, tlp=None):
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self.fmt = 0
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@ -1416,10 +1544,8 @@ class Function(PMCapability, PCIECapability):
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self.rx_cpl_sync = [Signal(False)]*256
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self.rx_tlp_handler = {}
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self.capabilities = {}
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self.last_capability_id = None
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self.ext_capabilities = {}
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self.last_ext_capability_id = None
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self.capabilities = PcieCapList()
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self.ext_capabilities = PcieExtCapList()
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# configuration registers
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self.vendor_id = 0
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@ -1556,131 +1682,26 @@ class Function(PMCapability, PCIECapability):
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elif 256 <= reg < 4096: self.write_extended_capability_register(reg, data, mask)
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def read_capability_register(self, reg):
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for cap in self.capabilities:
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if self.capabilities[cap][0] <= reg < self.capabilities[cap][0]+self.capabilities[cap][1]:
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print("read cap %d" % cap)
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offset = reg-self.capabilities[cap][0]
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val = self.capabilities[cap][2](offset)
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if offset == 0:
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val = (val & 0xffff0000) | (self.capabilities[cap][4] << 8) | cap
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return val
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return 0
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return self.capabilities.read_register(reg)
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def write_capability_register(self, reg, data, mask):
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for cap in self.capabilities:
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if self.capabilities[cap][0] <= reg < self.capabilities[cap][0]+self.capabilities[cap][1]:
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offset = reg-self.capabilities[cap][0]
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self.capabilities[cap][3](offset, data, mask)
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return
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self.capabilities.write_register(reg, data, mask)
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def register_capability(self, cap_id, length=None, read=None, write=None, offset=None):
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if cap_id in self.capabilities:
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# re-registering, capture and remove entry
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orig_offset = self.capabilities[cap_id][0]
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if not offset:
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offset = self.capabilities[cap_id][0]
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if not length:
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length = self.capabilities[cap_id][1]
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if not read:
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read = self.capabilities[cap_id][2]
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if not write:
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write = self.capabilities[cap_id][3]
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# remove from linked list
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if self.cap_ptr == orig_offset*4:
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self.cap_ptr = self.capabilities[cap_id][4]
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else:
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for cap in self.capabilities:
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if self.capabilities[cap][4] == orig_offset*4:
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self.capabilities[cap][4] = self.capabilities[cap_id][4]
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del self.capabilities[cap_id]
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elif not length or not read or not write:
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raise Exception("Missing required parameter")
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cl = sorted([(self.capabilities[x][0], self.capabilities[x][1]) for x in self.capabilities])
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if offset is not None:
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for a, l in cl:
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if a <= offset+length-1 and offset <= a+l-1:
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raise Exception("Invalid offset")
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self.capabilities.register(cap_id, 0, length, read, write, offset)
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if self.capabilities.list:
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self.cap_ptr = self.capabilities.list[0].offset*4
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else:
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offset = 0x10
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for a, l in cl:
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if a <= offset+length-1 and offset <= a+l-1:
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offset = a+l
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self.capabilities[cap_id] = [offset, length, read, write, 0]
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# add to linked list
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if self.last_capability_id is not None:
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self.capabilities[self.last_capability_id][4] = offset*4
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else:
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self.cap_ptr = offset*4
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self.last_capability_id = cap_id
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self.cap_ptr = 0
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def read_extended_capability_register(self, reg):
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for cap in self.ext_capabilities:
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if self.ext_capabilities[cap][0] <= reg < self.ext_capabilities[cap][0]+self.ext_capabilities[cap][1]:
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offset = reg-self.ext_capabilities[cap][0]
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if offset == 0:
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return (self.ext_capabilities[cap][4] << 20) | cap
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return self.ext_capabilities[cap][2](offset)
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return 0
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return self.ext_capabilities.read_register(reg)
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def write_extended_capability_register(self, reg, data, mask):
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for cap in self.ext_capabilities:
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if self.ext_capabilities[cap][0] <= reg < self.ext_capabilities[cap][0]+self.ext_capabilities[cap][1]:
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offset = reg-self.ext_capabilities[cap][0]
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self.ext_capabilities[cap][3](offset, data, mask)
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return
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self.ext_capabilities.write_register(reg, data, mask)
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def register_extended_capability(self, cap_id, cap_ver, length=None, read=None, write=None, offset=None):
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if cap_id in self.ext_capabilities:
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# re-registering, capture and remove entry
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orig_offset = self.ext_capabilities[cap_id][0]
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if not offset:
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offset = self.ext_capabilities[cap_id][0]
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if not length:
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length = self.ext_capabilities[cap_id][1]
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if not read:
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read = self.ext_capabilities[cap_id][2]
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if not write:
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write = self.ext_capabilities[cap_id][3]
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if not cap_ver:
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cap_ver = self.ext_capabilities[cap_id][5]
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# remove from linked list
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for cap in self.ext_capabilities:
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if self.ext_capabilities[cap][4] == orig_offset*4:
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self.ext_capabilities[cap][4] = self.ext_capabilities[cap_id][4]
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del self.ext_capabilities[cap_id]
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elif not length or not read or not write:
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raise Exception("Missing required parameter")
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cl = sorted([(self.ext_capabilities[x][0], self.ext_capabilities[x][1]) for x in self.ext_capabilities])
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if offset is not None:
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for a, l in cl:
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if a <= offset+length-1 and offset <= a+l-1:
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raise Exception("Invalid offset")
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else:
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offset = 0x40
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for a, l in cl:
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if a <= offset+length-1 and offset <= a+l-1:
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offset = a+l
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self.ext_capabilities[cap_id] = [offset, length, read, write, 0, cap_ver]
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# add to linked list
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if self.last_ext_capability_id is not None:
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self.ext_capabilities[self.last_ext_capability_id][4] = offset*4
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else:
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raise Exception("TODO")
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self.last_ext_capability_id = cap_id
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self.ext_capabilities.register(cap_id, cap_ver, length, read, write, offset)
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def configure_bar(self, idx, size, ext=False, prefetch=False, io=False):
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mask = 2**math.ceil(math.log(size, 2))-1
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