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Update python parameter computation to match verilog clog2

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This commit is contained in:
Alex Forencich 2019-11-24 00:01:33 -08:00
parent f6f8e556ef
commit 176e1159a3
18 changed files with 23 additions and 23 deletions
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2
tb/test_dma_client_axis_sink_128_64.py
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@ -48,7 +48,7 @@ def bench():
SEG_DATA_WIDTH = 64
SEG_ADDR_WIDTH = 12
SEG_BE_WIDTH = int(SEG_DATA_WIDTH/8)
RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+SEG_COUNT.bit_length()+SEG_BE_WIDTH.bit_length()
RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+(SEG_COUNT-1).bit_length()+(SEG_BE_WIDTH-1).bit_length()
AXIS_DATA_WIDTH = SEG_DATA_WIDTH*SEG_COUNT/2
AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8)
AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8)

2
tb/test_dma_client_axis_sink_512_64.py
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@ -48,7 +48,7 @@ def bench():
SEG_DATA_WIDTH = 128
SEG_ADDR_WIDTH = 12
SEG_BE_WIDTH = int(SEG_DATA_WIDTH/8)
RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+SEG_COUNT.bit_length()+SEG_BE_WIDTH.bit_length()
RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+(SEG_COUNT-1).bit_length()+(SEG_BE_WIDTH-1).bit_length()
AXIS_DATA_WIDTH = 64
AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8)
AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8)

2
tb/test_dma_client_axis_source_128_64.py
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@ -48,7 +48,7 @@ def bench():
SEG_DATA_WIDTH = 64
SEG_ADDR_WIDTH = 12
SEG_BE_WIDTH = int(SEG_DATA_WIDTH/8)
RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+SEG_COUNT.bit_length()+SEG_BE_WIDTH.bit_length()
RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+(SEG_COUNT-1).bit_length()+(SEG_BE_WIDTH-1).bit_length()
AXIS_DATA_WIDTH = SEG_DATA_WIDTH*SEG_COUNT/2
AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8)
AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8)

2
tb/test_dma_client_axis_source_512_64.py
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@ -48,7 +48,7 @@ def bench():
SEG_DATA_WIDTH = 128
SEG_ADDR_WIDTH = 12
SEG_BE_WIDTH = int(SEG_DATA_WIDTH/8)
RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+SEG_COUNT.bit_length()+SEG_BE_WIDTH.bit_length()
RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+(SEG_COUNT-1).bit_length()+(SEG_BE_WIDTH-1).bit_length()
AXIS_DATA_WIDTH = 64
AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8)
AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8)

4
tb/test_dma_if_pcie_us_256.py
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@ -59,10 +59,10 @@ def bench():
SEG_ADDR_WIDTH = 12
SEG_BE_WIDTH = int(SEG_DATA_WIDTH/8)
RAM_SEL_WIDTH = 2
RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+SEG_COUNT.bit_length()+SEG_BE_WIDTH.bit_length()
RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+(SEG_COUNT-1).bit_length()+(SEG_BE_WIDTH-1).bit_length()
PCIE_ADDR_WIDTH = 64
PCIE_TAG_COUNT = 64 if AXIS_PCIE_RQ_USER_WIDTH == 60 else 256
PCIE_TAG_WIDTH = PCIE_TAG_COUNT.bit_length()
PCIE_TAG_WIDTH = (PCIE_TAG_COUNT-1).bit_length()
PCIE_EXT_TAG_ENABLE = (PCIE_TAG_COUNT>32)
LEN_WIDTH = 16
TAG_WIDTH = 8

4
tb/test_dma_if_pcie_us_rd_128.py
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@ -57,10 +57,10 @@ def bench():
SEG_ADDR_WIDTH = 12
SEG_BE_WIDTH = int(SEG_DATA_WIDTH/8)
RAM_SEL_WIDTH = 2
RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+SEG_COUNT.bit_length()+SEG_BE_WIDTH.bit_length()
RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+(SEG_COUNT-1).bit_length()+(SEG_BE_WIDTH-1).bit_length()
PCIE_ADDR_WIDTH = 64
PCIE_TAG_COUNT = 64 if AXIS_PCIE_RQ_USER_WIDTH == 60 else 256
PCIE_TAG_WIDTH = PCIE_TAG_COUNT.bit_length()
PCIE_TAG_WIDTH = (PCIE_TAG_COUNT-1).bit_length()
PCIE_EXT_TAG_ENABLE = (PCIE_TAG_COUNT>32)
LEN_WIDTH = 16
TAG_WIDTH = 8

4
tb/test_dma_if_pcie_us_rd_256.py
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@ -57,10 +57,10 @@ def bench():
SEG_ADDR_WIDTH = 12
SEG_BE_WIDTH = int(SEG_DATA_WIDTH/8)
SEG_SEL_WIDTH = 2
RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+SEG_COUNT.bit_length()+SEG_BE_WIDTH.bit_length()
RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+(SEG_COUNT-1).bit_length()+(SEG_BE_WIDTH-1).bit_length()
PCIE_ADDR_WIDTH = 64
PCIE_TAG_COUNT = 64 if AXIS_PCIE_RQ_USER_WIDTH == 60 else 256
PCIE_TAG_WIDTH = PCIE_TAG_COUNT.bit_length()
PCIE_TAG_WIDTH = (PCIE_TAG_COUNT-1).bit_length()
PCIE_EXT_TAG_ENABLE = (PCIE_TAG_COUNT>32)
LEN_WIDTH = 16
TAG_WIDTH = 8

4
tb/test_dma_if_pcie_us_rd_512.py
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@ -57,10 +57,10 @@ def bench():
SEG_ADDR_WIDTH = 12
SEG_BE_WIDTH = int(SEG_DATA_WIDTH/8)
SEG_SEL_WIDTH = 2
RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+SEG_COUNT.bit_length()+SEG_BE_WIDTH.bit_length()
RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+(SEG_COUNT-1).bit_length()+(SEG_BE_WIDTH-1).bit_length()
PCIE_ADDR_WIDTH = 64
PCIE_TAG_COUNT = 64 if AXIS_PCIE_RQ_USER_WIDTH == 60 else 256
PCIE_TAG_WIDTH = PCIE_TAG_COUNT.bit_length()
PCIE_TAG_WIDTH = (PCIE_TAG_COUNT-1).bit_length()
PCIE_EXT_TAG_ENABLE = (PCIE_TAG_COUNT>32)
LEN_WIDTH = 16
TAG_WIDTH = 8

4
tb/test_dma_if_pcie_us_rd_64.py
View File

@ -57,10 +57,10 @@ def bench():
SEG_ADDR_WIDTH = 12
SEG_BE_WIDTH = int(SEG_DATA_WIDTH/8)
RAM_SEL_WIDTH = 2
RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+SEG_COUNT.bit_length()+SEG_BE_WIDTH.bit_length()
RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+(SEG_COUNT-1).bit_length()+(SEG_BE_WIDTH-1).bit_length()
PCIE_ADDR_WIDTH = 64
PCIE_TAG_COUNT = 64 if AXIS_PCIE_RQ_USER_WIDTH == 60 else 256
PCIE_TAG_WIDTH = PCIE_TAG_COUNT.bit_length()
PCIE_TAG_WIDTH = (PCIE_TAG_COUNT-1).bit_length()
PCIE_EXT_TAG_ENABLE = (PCIE_TAG_COUNT>32)
LEN_WIDTH = 16
TAG_WIDTH = 8

2
tb/test_dma_if_pcie_us_wr_128.py
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@ -54,7 +54,7 @@ def bench():
SEG_ADDR_WIDTH = 12
SEG_BE_WIDTH = int(SEG_DATA_WIDTH/8)
RAM_SEL_WIDTH = 2
RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+SEG_COUNT.bit_length()+SEG_BE_WIDTH.bit_length()
RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+(SEG_COUNT-1).bit_length()+(SEG_BE_WIDTH-1).bit_length()
PCIE_ADDR_WIDTH = 64
LEN_WIDTH = 16
TAG_WIDTH = 8

2
tb/test_dma_if_pcie_us_wr_256.py
View File

@ -54,7 +54,7 @@ def bench():
SEG_ADDR_WIDTH = 12
SEG_BE_WIDTH = int(SEG_DATA_WIDTH/8)
RAM_SEL_WIDTH = 2
RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+SEG_COUNT.bit_length()+SEG_BE_WIDTH.bit_length()
RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+(SEG_COUNT-1).bit_length()+(SEG_BE_WIDTH-1).bit_length()
PCIE_ADDR_WIDTH = 64
LEN_WIDTH = 16
TAG_WIDTH = 8

2
tb/test_dma_if_pcie_us_wr_512.py
View File

@ -54,7 +54,7 @@ def bench():
SEG_ADDR_WIDTH = 12
SEG_BE_WIDTH = int(SEG_DATA_WIDTH/8)
RAM_SEL_WIDTH = 2
RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+SEG_COUNT.bit_length()+SEG_BE_WIDTH.bit_length()
RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+(SEG_COUNT-1).bit_length()+(SEG_BE_WIDTH-1).bit_length()
PCIE_ADDR_WIDTH = 64
LEN_WIDTH = 16
TAG_WIDTH = 8

2
tb/test_dma_if_pcie_us_wr_64.py
View File

@ -54,7 +54,7 @@ def bench():
SEG_ADDR_WIDTH = 12
SEG_BE_WIDTH = int(SEG_DATA_WIDTH/8)
RAM_SEL_WIDTH = 2
RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+SEG_COUNT.bit_length()+SEG_BE_WIDTH.bit_length()
RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+(SEG_COUNT-1).bit_length()+(SEG_BE_WIDTH-1).bit_length()
PCIE_ADDR_WIDTH = 64
LEN_WIDTH = 16
TAG_WIDTH = 8

2
tb/test_pcie_us_axi_dma_256.py
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@ -61,7 +61,7 @@ def bench():
AXI_MAX_BURST_LEN = 256
PCIE_ADDR_WIDTH = 64
PCIE_TAG_COUNT = 64 if AXIS_PCIE_RQ_USER_WIDTH == 60 else 256
PCIE_TAG_WIDTH = PCIE_TAG_COUNT.bit_length()
PCIE_TAG_WIDTH = (PCIE_TAG_COUNT-1).bit_length()
PCIE_EXT_TAG_ENABLE = 1
LEN_WIDTH = 20
TAG_WIDTH = 8

2
tb/test_pcie_us_axi_dma_rd_128.py
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@ -60,7 +60,7 @@ def bench():
AXI_MAX_BURST_LEN = 256
PCIE_ADDR_WIDTH = 64
PCIE_TAG_COUNT = 64 if AXIS_PCIE_RQ_USER_WIDTH == 60 else 256
PCIE_TAG_WIDTH = PCIE_TAG_COUNT.bit_length()
PCIE_TAG_WIDTH = (PCIE_TAG_COUNT-1).bit_length()
PCIE_EXT_TAG_ENABLE = 1
LEN_WIDTH = 20
TAG_WIDTH = 8

2
tb/test_pcie_us_axi_dma_rd_256.py
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@ -60,7 +60,7 @@ def bench():
AXI_MAX_BURST_LEN = 256
PCIE_ADDR_WIDTH = 64
PCIE_TAG_COUNT = 64 if AXIS_PCIE_RQ_USER_WIDTH == 60 else 256
PCIE_TAG_WIDTH = PCIE_TAG_COUNT.bit_length()
PCIE_TAG_WIDTH = (PCIE_TAG_COUNT-1).bit_length()
PCIE_EXT_TAG_ENABLE = 1
LEN_WIDTH = 20
TAG_WIDTH = 8

2
tb/test_pcie_us_axi_dma_rd_512.py
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@ -60,7 +60,7 @@ def bench():
AXI_MAX_BURST_LEN = 256
PCIE_ADDR_WIDTH = 64
PCIE_TAG_COUNT = 64 if AXIS_PCIE_RQ_USER_WIDTH == 60 else 256
PCIE_TAG_WIDTH = PCIE_TAG_COUNT.bit_length()
PCIE_TAG_WIDTH = (PCIE_TAG_COUNT-1).bit_length()
PCIE_EXT_TAG_ENABLE = 1
LEN_WIDTH = 20
TAG_WIDTH = 8

2
tb/test_pcie_us_axi_dma_rd_64.py
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@ -60,7 +60,7 @@ def bench():
AXI_MAX_BURST_LEN = 256
PCIE_ADDR_WIDTH = 64
PCIE_TAG_COUNT = 64 if AXIS_PCIE_RQ_USER_WIDTH == 60 else 256
PCIE_TAG_WIDTH = PCIE_TAG_COUNT.bit_length()
PCIE_TAG_WIDTH = (PCIE_TAG_COUNT-1).bit_length()
PCIE_EXT_TAG_ENABLE = 1
LEN_WIDTH = 20
TAG_WIDTH = 8