diff --git a/tb/test_dma_client_axis_sink_128_64.py b/tb/test_dma_client_axis_sink_128_64.py index 7281833..036bbad 100755 --- a/tb/test_dma_client_axis_sink_128_64.py +++ b/tb/test_dma_client_axis_sink_128_64.py @@ -48,7 +48,7 @@ def bench(): SEG_DATA_WIDTH = 64 SEG_ADDR_WIDTH = 12 SEG_BE_WIDTH = int(SEG_DATA_WIDTH/8) - RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+SEG_COUNT.bit_length()+SEG_BE_WIDTH.bit_length() + RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+(SEG_COUNT-1).bit_length()+(SEG_BE_WIDTH-1).bit_length() AXIS_DATA_WIDTH = SEG_DATA_WIDTH*SEG_COUNT/2 AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8) AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8) diff --git a/tb/test_dma_client_axis_sink_512_64.py b/tb/test_dma_client_axis_sink_512_64.py index 49a8985..da8e614 100755 --- a/tb/test_dma_client_axis_sink_512_64.py +++ b/tb/test_dma_client_axis_sink_512_64.py @@ -48,7 +48,7 @@ def bench(): SEG_DATA_WIDTH = 128 SEG_ADDR_WIDTH = 12 SEG_BE_WIDTH = int(SEG_DATA_WIDTH/8) - RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+SEG_COUNT.bit_length()+SEG_BE_WIDTH.bit_length() + RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+(SEG_COUNT-1).bit_length()+(SEG_BE_WIDTH-1).bit_length() AXIS_DATA_WIDTH = 64 AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8) AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8) diff --git a/tb/test_dma_client_axis_source_128_64.py b/tb/test_dma_client_axis_source_128_64.py index ae2ef70..c5ea889 100755 --- a/tb/test_dma_client_axis_source_128_64.py +++ b/tb/test_dma_client_axis_source_128_64.py @@ -48,7 +48,7 @@ def bench(): SEG_DATA_WIDTH = 64 SEG_ADDR_WIDTH = 12 SEG_BE_WIDTH = int(SEG_DATA_WIDTH/8) - RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+SEG_COUNT.bit_length()+SEG_BE_WIDTH.bit_length() + RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+(SEG_COUNT-1).bit_length()+(SEG_BE_WIDTH-1).bit_length() AXIS_DATA_WIDTH = SEG_DATA_WIDTH*SEG_COUNT/2 AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8) AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8) diff --git a/tb/test_dma_client_axis_source_512_64.py b/tb/test_dma_client_axis_source_512_64.py index 642b7a6..a188c70 100755 --- a/tb/test_dma_client_axis_source_512_64.py +++ b/tb/test_dma_client_axis_source_512_64.py @@ -48,7 +48,7 @@ def bench(): SEG_DATA_WIDTH = 128 SEG_ADDR_WIDTH = 12 SEG_BE_WIDTH = int(SEG_DATA_WIDTH/8) - RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+SEG_COUNT.bit_length()+SEG_BE_WIDTH.bit_length() + RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+(SEG_COUNT-1).bit_length()+(SEG_BE_WIDTH-1).bit_length() AXIS_DATA_WIDTH = 64 AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8) AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8) diff --git a/tb/test_dma_if_pcie_us_256.py b/tb/test_dma_if_pcie_us_256.py index c729b54..2973596 100755 --- a/tb/test_dma_if_pcie_us_256.py +++ b/tb/test_dma_if_pcie_us_256.py @@ -59,10 +59,10 @@ def bench(): SEG_ADDR_WIDTH = 12 SEG_BE_WIDTH = int(SEG_DATA_WIDTH/8) RAM_SEL_WIDTH = 2 - RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+SEG_COUNT.bit_length()+SEG_BE_WIDTH.bit_length() + RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+(SEG_COUNT-1).bit_length()+(SEG_BE_WIDTH-1).bit_length() PCIE_ADDR_WIDTH = 64 PCIE_TAG_COUNT = 64 if AXIS_PCIE_RQ_USER_WIDTH == 60 else 256 - PCIE_TAG_WIDTH = PCIE_TAG_COUNT.bit_length() + PCIE_TAG_WIDTH = (PCIE_TAG_COUNT-1).bit_length() PCIE_EXT_TAG_ENABLE = (PCIE_TAG_COUNT>32) LEN_WIDTH = 16 TAG_WIDTH = 8 diff --git a/tb/test_dma_if_pcie_us_rd_128.py b/tb/test_dma_if_pcie_us_rd_128.py index f9c5859..934ddf1 100755 --- a/tb/test_dma_if_pcie_us_rd_128.py +++ b/tb/test_dma_if_pcie_us_rd_128.py @@ -57,10 +57,10 @@ def bench(): SEG_ADDR_WIDTH = 12 SEG_BE_WIDTH = int(SEG_DATA_WIDTH/8) RAM_SEL_WIDTH = 2 - RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+SEG_COUNT.bit_length()+SEG_BE_WIDTH.bit_length() + RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+(SEG_COUNT-1).bit_length()+(SEG_BE_WIDTH-1).bit_length() PCIE_ADDR_WIDTH = 64 PCIE_TAG_COUNT = 64 if AXIS_PCIE_RQ_USER_WIDTH == 60 else 256 - PCIE_TAG_WIDTH = PCIE_TAG_COUNT.bit_length() + PCIE_TAG_WIDTH = (PCIE_TAG_COUNT-1).bit_length() PCIE_EXT_TAG_ENABLE = (PCIE_TAG_COUNT>32) LEN_WIDTH = 16 TAG_WIDTH = 8 diff --git a/tb/test_dma_if_pcie_us_rd_256.py b/tb/test_dma_if_pcie_us_rd_256.py index 657f072..cc422e6 100755 --- a/tb/test_dma_if_pcie_us_rd_256.py +++ b/tb/test_dma_if_pcie_us_rd_256.py @@ -57,10 +57,10 @@ def bench(): SEG_ADDR_WIDTH = 12 SEG_BE_WIDTH = int(SEG_DATA_WIDTH/8) SEG_SEL_WIDTH = 2 - RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+SEG_COUNT.bit_length()+SEG_BE_WIDTH.bit_length() + RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+(SEG_COUNT-1).bit_length()+(SEG_BE_WIDTH-1).bit_length() PCIE_ADDR_WIDTH = 64 PCIE_TAG_COUNT = 64 if AXIS_PCIE_RQ_USER_WIDTH == 60 else 256 - PCIE_TAG_WIDTH = PCIE_TAG_COUNT.bit_length() + PCIE_TAG_WIDTH = (PCIE_TAG_COUNT-1).bit_length() PCIE_EXT_TAG_ENABLE = (PCIE_TAG_COUNT>32) LEN_WIDTH = 16 TAG_WIDTH = 8 diff --git a/tb/test_dma_if_pcie_us_rd_512.py b/tb/test_dma_if_pcie_us_rd_512.py index c6da8f0..b150d2a 100755 --- a/tb/test_dma_if_pcie_us_rd_512.py +++ b/tb/test_dma_if_pcie_us_rd_512.py @@ -57,10 +57,10 @@ def bench(): SEG_ADDR_WIDTH = 12 SEG_BE_WIDTH = int(SEG_DATA_WIDTH/8) SEG_SEL_WIDTH = 2 - RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+SEG_COUNT.bit_length()+SEG_BE_WIDTH.bit_length() + RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+(SEG_COUNT-1).bit_length()+(SEG_BE_WIDTH-1).bit_length() PCIE_ADDR_WIDTH = 64 PCIE_TAG_COUNT = 64 if AXIS_PCIE_RQ_USER_WIDTH == 60 else 256 - PCIE_TAG_WIDTH = PCIE_TAG_COUNT.bit_length() + PCIE_TAG_WIDTH = (PCIE_TAG_COUNT-1).bit_length() PCIE_EXT_TAG_ENABLE = (PCIE_TAG_COUNT>32) LEN_WIDTH = 16 TAG_WIDTH = 8 diff --git a/tb/test_dma_if_pcie_us_rd_64.py b/tb/test_dma_if_pcie_us_rd_64.py index 54d5bd5..2d86ddb 100755 --- a/tb/test_dma_if_pcie_us_rd_64.py +++ b/tb/test_dma_if_pcie_us_rd_64.py @@ -57,10 +57,10 @@ def bench(): SEG_ADDR_WIDTH = 12 SEG_BE_WIDTH = int(SEG_DATA_WIDTH/8) RAM_SEL_WIDTH = 2 - RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+SEG_COUNT.bit_length()+SEG_BE_WIDTH.bit_length() + RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+(SEG_COUNT-1).bit_length()+(SEG_BE_WIDTH-1).bit_length() PCIE_ADDR_WIDTH = 64 PCIE_TAG_COUNT = 64 if AXIS_PCIE_RQ_USER_WIDTH == 60 else 256 - PCIE_TAG_WIDTH = PCIE_TAG_COUNT.bit_length() + PCIE_TAG_WIDTH = (PCIE_TAG_COUNT-1).bit_length() PCIE_EXT_TAG_ENABLE = (PCIE_TAG_COUNT>32) LEN_WIDTH = 16 TAG_WIDTH = 8 diff --git a/tb/test_dma_if_pcie_us_wr_128.py b/tb/test_dma_if_pcie_us_wr_128.py index c9f3623..44a1300 100755 --- a/tb/test_dma_if_pcie_us_wr_128.py +++ b/tb/test_dma_if_pcie_us_wr_128.py @@ -54,7 +54,7 @@ def bench(): SEG_ADDR_WIDTH = 12 SEG_BE_WIDTH = int(SEG_DATA_WIDTH/8) RAM_SEL_WIDTH = 2 - RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+SEG_COUNT.bit_length()+SEG_BE_WIDTH.bit_length() + RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+(SEG_COUNT-1).bit_length()+(SEG_BE_WIDTH-1).bit_length() PCIE_ADDR_WIDTH = 64 LEN_WIDTH = 16 TAG_WIDTH = 8 diff --git a/tb/test_dma_if_pcie_us_wr_256.py b/tb/test_dma_if_pcie_us_wr_256.py index e263178..7302d68 100755 --- a/tb/test_dma_if_pcie_us_wr_256.py +++ b/tb/test_dma_if_pcie_us_wr_256.py @@ -54,7 +54,7 @@ def bench(): SEG_ADDR_WIDTH = 12 SEG_BE_WIDTH = int(SEG_DATA_WIDTH/8) RAM_SEL_WIDTH = 2 - RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+SEG_COUNT.bit_length()+SEG_BE_WIDTH.bit_length() + RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+(SEG_COUNT-1).bit_length()+(SEG_BE_WIDTH-1).bit_length() PCIE_ADDR_WIDTH = 64 LEN_WIDTH = 16 TAG_WIDTH = 8 diff --git a/tb/test_dma_if_pcie_us_wr_512.py b/tb/test_dma_if_pcie_us_wr_512.py index a34d86e..a3dc160 100755 --- a/tb/test_dma_if_pcie_us_wr_512.py +++ b/tb/test_dma_if_pcie_us_wr_512.py @@ -54,7 +54,7 @@ def bench(): SEG_ADDR_WIDTH = 12 SEG_BE_WIDTH = int(SEG_DATA_WIDTH/8) RAM_SEL_WIDTH = 2 - RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+SEG_COUNT.bit_length()+SEG_BE_WIDTH.bit_length() + RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+(SEG_COUNT-1).bit_length()+(SEG_BE_WIDTH-1).bit_length() PCIE_ADDR_WIDTH = 64 LEN_WIDTH = 16 TAG_WIDTH = 8 diff --git a/tb/test_dma_if_pcie_us_wr_64.py b/tb/test_dma_if_pcie_us_wr_64.py index db4969b..a917f42 100755 --- a/tb/test_dma_if_pcie_us_wr_64.py +++ b/tb/test_dma_if_pcie_us_wr_64.py @@ -54,7 +54,7 @@ def bench(): SEG_ADDR_WIDTH = 12 SEG_BE_WIDTH = int(SEG_DATA_WIDTH/8) RAM_SEL_WIDTH = 2 - RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+SEG_COUNT.bit_length()+SEG_BE_WIDTH.bit_length() + RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+(SEG_COUNT-1).bit_length()+(SEG_BE_WIDTH-1).bit_length() PCIE_ADDR_WIDTH = 64 LEN_WIDTH = 16 TAG_WIDTH = 8 diff --git a/tb/test_pcie_us_axi_dma_256.py b/tb/test_pcie_us_axi_dma_256.py index 7802cfa..0eef694 100755 --- a/tb/test_pcie_us_axi_dma_256.py +++ b/tb/test_pcie_us_axi_dma_256.py @@ -61,7 +61,7 @@ def bench(): AXI_MAX_BURST_LEN = 256 PCIE_ADDR_WIDTH = 64 PCIE_TAG_COUNT = 64 if AXIS_PCIE_RQ_USER_WIDTH == 60 else 256 - PCIE_TAG_WIDTH = PCIE_TAG_COUNT.bit_length() + PCIE_TAG_WIDTH = (PCIE_TAG_COUNT-1).bit_length() PCIE_EXT_TAG_ENABLE = 1 LEN_WIDTH = 20 TAG_WIDTH = 8 diff --git a/tb/test_pcie_us_axi_dma_rd_128.py b/tb/test_pcie_us_axi_dma_rd_128.py index 38c3e32..b18426a 100755 --- a/tb/test_pcie_us_axi_dma_rd_128.py +++ b/tb/test_pcie_us_axi_dma_rd_128.py @@ -60,7 +60,7 @@ def bench(): AXI_MAX_BURST_LEN = 256 PCIE_ADDR_WIDTH = 64 PCIE_TAG_COUNT = 64 if AXIS_PCIE_RQ_USER_WIDTH == 60 else 256 - PCIE_TAG_WIDTH = PCIE_TAG_COUNT.bit_length() + PCIE_TAG_WIDTH = (PCIE_TAG_COUNT-1).bit_length() PCIE_EXT_TAG_ENABLE = 1 LEN_WIDTH = 20 TAG_WIDTH = 8 diff --git a/tb/test_pcie_us_axi_dma_rd_256.py b/tb/test_pcie_us_axi_dma_rd_256.py index d8e619c..b2b5c3d 100755 --- a/tb/test_pcie_us_axi_dma_rd_256.py +++ b/tb/test_pcie_us_axi_dma_rd_256.py @@ -60,7 +60,7 @@ def bench(): AXI_MAX_BURST_LEN = 256 PCIE_ADDR_WIDTH = 64 PCIE_TAG_COUNT = 64 if AXIS_PCIE_RQ_USER_WIDTH == 60 else 256 - PCIE_TAG_WIDTH = PCIE_TAG_COUNT.bit_length() + PCIE_TAG_WIDTH = (PCIE_TAG_COUNT-1).bit_length() PCIE_EXT_TAG_ENABLE = 1 LEN_WIDTH = 20 TAG_WIDTH = 8 diff --git a/tb/test_pcie_us_axi_dma_rd_512.py b/tb/test_pcie_us_axi_dma_rd_512.py index 5811a09..aa35f37 100755 --- a/tb/test_pcie_us_axi_dma_rd_512.py +++ b/tb/test_pcie_us_axi_dma_rd_512.py @@ -60,7 +60,7 @@ def bench(): AXI_MAX_BURST_LEN = 256 PCIE_ADDR_WIDTH = 64 PCIE_TAG_COUNT = 64 if AXIS_PCIE_RQ_USER_WIDTH == 60 else 256 - PCIE_TAG_WIDTH = PCIE_TAG_COUNT.bit_length() + PCIE_TAG_WIDTH = (PCIE_TAG_COUNT-1).bit_length() PCIE_EXT_TAG_ENABLE = 1 LEN_WIDTH = 20 TAG_WIDTH = 8 diff --git a/tb/test_pcie_us_axi_dma_rd_64.py b/tb/test_pcie_us_axi_dma_rd_64.py index a1de1be..fc5a6fa 100755 --- a/tb/test_pcie_us_axi_dma_rd_64.py +++ b/tb/test_pcie_us_axi_dma_rd_64.py @@ -60,7 +60,7 @@ def bench(): AXI_MAX_BURST_LEN = 256 PCIE_ADDR_WIDTH = 64 PCIE_TAG_COUNT = 64 if AXIS_PCIE_RQ_USER_WIDTH == 60 else 256 - PCIE_TAG_WIDTH = PCIE_TAG_COUNT.bit_length() + PCIE_TAG_WIDTH = (PCIE_TAG_COUNT-1).bit_length() PCIE_EXT_TAG_ENABLE = 1 LEN_WIDTH = 20 TAG_WIDTH = 8