FPGA/verilog-pcie
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Fix part-select range

Browse Source
This commit is contained in:
Alex Forencich 2019-10-01 22:00:03 -07:00
parent 295b6a507e
commit 1b98af9364
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
rtl/pcie_us_axi_master_rd.v
View File

@ -642,7 +642,7 @@ always @* begin
end
m_axis_cc_tuser_int[0] = 1'b0; // discontinue
m_axis_cc_tuser_int[33:1] = 32'd0; // parity
m_axis_cc_tuser_int[32:1] = 32'd0; // parity
// AXI read response processing and TLP generation
case (tlp_state_reg)