FPGA/verilog-pcie
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Always ready on RC channel in idle for 64 bits

Browse Source
This commit is contained in:
Alex Forencich 2019-01-22 23:00:17 -08:00
parent 4422b908bf
commit 201c5faa80
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
rtl/pcie_us_axi_dma_rd.v
View File

@ -725,14 +725,14 @@ always @* begin
end
if (s_axis_rc_tlast) begin
s_axis_rc_tready_next = !m_axi_awvalid || m_axi_awready;
s_axis_rc_tready_next = 1'b1;
tlp_state_next = TLP_STATE_IDLE;
end else begin
s_axis_rc_tready_next = 1'b0;
tlp_state_next = TLP_STATE_HEADER;
end
end else begin
s_axis_rc_tready_next = !m_axi_awvalid || m_axi_awready;
s_axis_rc_tready_next = 1'b1;
tlp_state_next = TLP_STATE_IDLE;
end
end